Design and analysis of RF-low power and low-phase noise CMOS ring oscillator for fully integrated RF communication systems technologies

This manuscript presents the design and analysis of five-stage, low power ring oscillator. The ring oscillator has implemented in 0.18 μm CMOS one-poly six-metal-layer process technology and designed for frequency synthesiser module used in RF communication applications. This work uses a single ended topology and the delay cell is designed with both tail-ahead and tail-current concept for frequency improvement. This work projects the effect of transistor size (w/l) on the important parameters of oscillator viz. frequency and power dissipation. Measurements show that the oscillator covers a frequency range of 0.9-2 GHz. Their analyses demonstrate that the circuit consumes minimum power of 305 μW at 0.9 GHz and maximum 575 μW at 2 GHz oscillating frequency. The designed oscillator occupies an area of 296∗ 130 μm2 and manifest an improved phase noise level of -111.9 dBc/Hz. © 2016 Inderscience Enterprises Ltd.