Optimal design for FPGA interconnect based on combinations of single-driver and multi-driver wires

被引：0
|
作者：
Li W. [1 ,2 ]
Yang H.-G. [1 ]
Huang J. [1 ,2 ]
机构：
[1] Institute of Electronics, Chinese Academy of Sciences
[2] Graduate University of Chinese Academy of Sciences
来源：
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2010年 / 32卷 / 08期
关键词：
Area-delay product; FPGA; Interconnect; Multi-driver; Single-driver;
D O I：
10.3724/SP.J.1146.2009.01007
中图分类号：
学科分类号：
摘要：
Single-driver directional wires and multi-driver directional wires can both be used for FPGA interconnect. This paper compares them in area, performance, and their effect on topology of the routing architecture. Then a new type of FPGA routing architecture is proposed that utilizes a mixture of single-driver and multi-driver wires combined with various wire lengths and a two-stage optimization method is used to obtain the best routing architecture. Extensive experiments show that the best architecture optimized by area-delay product is 50% length 6 wires with single-driver, 25% length 8 wires with multi-driver and 25% length 8 wires with single-driver. This results in FPGA with 57%~86% gain in area-delay product.
引用
收藏
页码：2023 / 2027
页数：4
相关论文
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