Characterization of sub-100 nm MOSFETs with high K gate dielectric

被引：0

作者：

Zhu, Hui-Wen ^{[1
]}

Liu, Xiao-Yan ^{[1
]}

Shen, Chao ^{[1
]}

Kang, Jin-Feng ^{[1
]}

Han, Ru-Qi ^{[1
]}

机构：

[1] Inst. of Microelectron., Peking Univ., Beijing 100871, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2001年 / 22卷 / 09期

关键词：

Gate dielectrics - Short channel performance;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

(Edited Abstract)

引用

页码：1107 / 1111

共 50 条

[21] Facile Nanocasting of Dielectric Metasurfaces with Sub-100 nm Resolution
Kim, Kwan
Yoon, Gwanho
Baek, Seungho
Rho, Junsuk
Lee, Heon
ACS APPLIED MATERIALS & INTERFACES, 2019, 11 (29) : 26109 - 26115
[22] Radio-frequency performance of a sub-100 nm metal-oxide field-effect transistor with high-k gate dielectric
Kakushima, K.
Nakagawa, M.
Ahmet, P.
Tsutsui, K.
Sugii, N.
Hattori, T.
Iwai, H.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2010, 25 (04)
[23] Extending gate dielectric scaling limit by NO oxynitride: Design and process issues for sub-100 nm technology
Fujiwara, M
Takayanagi, M
Shimizu, T
Toyoshima, Y
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 227 - 230
[24] Double pocket architecture using indium and boron for sub-100 nm MOSFETs
Odanaka, S
Hiroki, A
Yamashita, K
Nakanishi, K
Noda, T
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (07) : 330 - 332
[25] Numerical Investigation of excess RF channel noise in sub-100 nm MOSFETs
Mahajan, Vinayak M.
Jindal, R. P.
Shichijo, Hisashi
Martin, S.
Hou, Fan-Chi
Trombley, Django
2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY, 2009, : 161 - +
[26] Monte Carlo simulations of sub-100 nm InGaAs MOSFETs for digital applications
Kalna, K
Yang, L
Asenov, A
PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 169 - 172
[27] High-Frequency Noise Measurements on MOSFETs with Channel-Lengths in Sub-100 nm regime
Patalay, Pradeep R.
Jindal, R. P.
Shichijo, Hisashi
Martin, S.
Hou, Fan-Chi
Trombley, Django
2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY, 2009, : 172 - +
[28] Undulation of sub-100 nm porous dielectric structures: A mechanical analysis
Darnon, M.
Chevolleau, T.
Joubert, O.
Maitrejean, S.
Barbe, J. C.
Torres, J.
APPLIED PHYSICS LETTERS, 2007, 91 (19)
[29] High performance sub-100 nm nitride/oxynitride stack gate dielectric CMOS device with refractory W/TiN metal gates
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Pan Tao Ti Hsueh Pao, 2006, 3 (448-453):
[30] Ultrafast Pulse Characterization of Hot Carrier Injection Effects on Ballistic Carrier Transport for Sub-100 nm MOSFETs
Cheng, Ran
Yu, Xiao
Shen, Lei
Yin, Longxiang
Zhang, Yanyan
Zheng, Zejie
Chen, Bing
Liu, Xiaoyan
Zhao, Yi
2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2017,

← 1 2 3 4 5 →