Design and Implementation of Configurable Cache Coherence Protocol for Multi- Core Processor

被引：0
|
作者：
Chen Z. [1 ]
Zhou H. [1 ]
Feng Q. [1 ]
Deng R. [1 ]
机构：
[1] College of Computer Science and Technology, National University of Defense Technology, Changsha
来源：
Zhou, Hongwei (forrestszhw@sohu.com) | 1600年 / Science Press卷 / 58期
关键词：
Coherence protocol; Configurable; Deadlock; Fault-tolerance; Multi-core processor;
D O I：
10.7544/issn1000-1239.2021.20210174
中图分类号：
学科分类号：
摘要：
In multi-core system, it is necessary to maintain the consistency of cache. Common cache coherence protocols can be divided into snoop-based protocol and directory-based protocol. Directory-based protocol has better scalability, lower latency and can be applied to more applications. According to the size of the directory, it can be divided into centralized directory and distributed directory. Distributed directory takes up less space and less time to inquiry. However, it's hard to design and verify cache coherence based on distributed directory. To reduce the risk in designing CPU, a configurable distribute directory unit (CDDU) is proposed. It increases the flexibility and fault tolerance of the multi-core system by the way of changing state transformation and protocol flow. The special design can protect system from design defects that may lead to severe error, and it shows good performance in dealing with deadlock problems caused by cache coherence. It provides considerable fault-tolerance that can give the designer more freedom and opportunity. The simulation result indicates that it provides considerable scalability and prevents the occurrence of potential deadlock at the cost of subtle performance loss and area expense. The methodology mentioned in this paper has been used in the design of 64-core FT processor, which ensures the correctness of cache coherence protocol without totally modifying the initial design.Moreover, it improves the robustness of the protocol and eliminates the potential deadlock with a subtle impact on system performance. © 2021, Science Press. All right reserved.
引用
收藏
页码：1166 / 1175
页数：9
相关论文
共 22 条
  • [1] Martin M M K, Hill M D, Sorin D J., Why on-chip cache coherence is here to stay, Communications of the ACM, 55, 7, pp. 78-89, (2012)
  • [2] Agarwal A, Simoni R, Horowitz M, Et al., An evaluation of directory schemes for cache coherence, Proc of the 15th Annual Int Symp on Computer Architecture, pp. 280-298, (1988)
  • [3] Acacio M E, Gonzlez J, Garca J M, Et al., A new scalable directory architecture for large-scale multiprocessors, Proc of the 7th Int Symp on High Performance Computer Architecture, pp. 97-106, (2001)
  • [4] Ferdman M, Lotfi-Kamran P, Balet K, Et al., Cuckoo directory: A scalable directory for many-core systems, Proc of the 17th Int Symp on High-Performance Computer Architecture, pp. 169-180, (2011)
  • [5] Guo Songliu, Wang Haixia, Xue Yibo, Et al., Hierarchical cache directory for CMP, Journal of Computer Science & Technology, 25, 2, pp. 246-256, (2010)
  • [6] Chang Y, Bhuyan L N., An efficient tree cache coherence protocol for distributed shared memory multiprocessors, IEEE Transactions on Computers, 48, 3, pp. 352-360, (1999)
  • [7] Kommrusch S, Horro M, Pouchet L N, Et al., Optimizing coherence traffic in manycore processors using closed-form caching/home agent mappings, IEEE Access, 9, pp. 28930-28945, (2021)
  • [8] Horro M, Kandemir M T, Pouchet L N, Et al., Effect of distributed directories in mesh interconnects, Proc of the 56th ACM/IEEE Design Automation Conf, pp. 1-6, (2019)
  • [9] Sodani A, Gramunt R, Corbal J, Et al., Knights landing: Second-Generation Intel Xeon Phi Product, IEEE Micro, 36, 2, pp. 34-46, (2016)
  • [10] Zhang Meng, Lebeck A R, Sorin D J., Fractal coherence: Scalably verifiable cache coherence, Proc of the 43rd Annual IEEE/ACM Int Symp on Microarchitecture, pp. 471-482, (2010)
123