Design of ternary adiabatic counter on switch-level

A novel design of ternary adiabatic counter using switch-level design techniques was presented to reduce the power consumption of multi-valued logic circuits. First, by analyzing the working principles and structures of multi-valued counter, the switch-level functional expressions of ternary adiabatic counter which consists of flip-flop, loop operation circuit and carry circuit were derived under the guidance of Three Essential Circuit Elements theory. Then, the four bits ternary adiabatic counter can be realized further by using cross-memory structure and NMOS transistors with different thresholds. Finally, the proposed counter was simulated by PSPICE and the results show that it has correct logic function and distinctive low power dissipation.