High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology

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作者：

Ker, Ming-Dou ^{[1
]}

Chang, Chyh-Yih ^{[2
]}

机构：

[1] Ker, Ming-Dou

[2] Chang, Chyh-Yih

来源：

Ker, M.-D. | 1600年 / Japan Society of Applied Physics卷 / 42期

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共 15 条

[1] High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology
Ker, MD
Chang, CY
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2003, 42 (6A): : 3377 - 3378
[2] Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
Ker, MD
Tseng, TK
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2004, 43 (1A-B): : L33 - L35
[3] Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process
Ker, M.-D. (mdker@ieee.org), 1600, Japan Society of Applied Physics (43):
[4] THE IMPACT OF NITROGEN IMPLANTATION INTO HIGHLY DOPED POLYSILICON GATES FOR HIGHLY RELIABLE AND HIGH-PERFORMANCE SUB-QUARTER-MICRON DUAL-GATE COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR
KUROI, T
KOBAYASHI, M
SHIRAHATA, M
OKUMURA, Y
KUSUNOKI, S
INUISHI, M
TSUBOUCHI, N
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1995, 34 (2B): : 771 - 775
[5] Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
Ker, M.-D. (mdker@ieee.org), 1600, Japan Society of Applied Physics (41):
[6] Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
Ker, MD
Hsu, HC
Peng, JJ
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2002, 41 (11B): : L1288 - L1290
[7] Performance Analysis of Ultra deep sub micron and Deep Sub Micron technology using Complementary Metal Oxide Semiconductor inverter
Soni, Upendra
Akashe, Shyam
7TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO 2013), 2013, : 290 - 294
[8] Effect of wet etched thickness and reoxidation on reliability of dual gate oxide for sub-quarter micron complementary metal-oxide-semiconductor devices
Cho, IH
Sung, NK
Oh, JH
Park, MS
Sohn, DK
Park, JW
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (4B): : 2167 - 2171
[9] Diode and RC Co-Triggered 2xVDD-Tolerant Electrostatic Discharge Detection Circuit in Nanoscale Complementary Metal-Oxide-Semiconductor Technology
Yang, Zhaonian
Yang, Yuan
Jing, Kai
Yu, Ningmei
Liou, Juin J.
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2019, 14 (05) : 734 - 739
[10] Characterization of dopant interdiffusion and power reduction on TiSi2 local wiring technology in sub-half-micron complementary metal oxide semiconductor
Ida, Jiro
Ohtomo, Atsushi
Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, 1998, 37 (4 A): : 1674 - 1679

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