A 10 Gb/s combined equalizer in 0.18 μm CMOS technology for backplane communication

被引：0

作者：

Zhang, Mingke ^{[1
]}

Hu, Qingsheng ^{[1
]}

机构：

[1] Institute of RF- & OE-ICs, Southeast University, Nanjing

来源：

High Technology Letters | 2015年 / 21卷 / 02期

关键词：

Analog equalizer; Current mode logic (CML); Decision feedback equalizer (DFE); Inductive peaking;

D O I：

10.3772/j.issn.1006-6748.2015.02.013

中图分类号：

学科分类号：

摘要：

This paper presents a 10 Gb/s high-speed equalizer as the front-end of a receiver for backplane communication. The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol-interference (ISI) of the communication channel. By employing inductive peaking technique for the high-frequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops (DFF) and multiplex (MUX), shortening the feedback path delay and speeding up the operation considerably. Designed in the 0.18 μm CMOS technology, the equalizer delivers 10 Gb/s data over 18-in FR4 trace with 28-dB loss while drawing 27-mW from a 1.8-V supply. The overall chip area including pads is 0.6×0.7 mm2. ©, 2015, Inst. of Scientific and Technical Information of China. All right reserved.

引用

页码：205 / 211

页数：6

共 10 条

[1]

Song S., Stojanovic V., A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links, IEEE J. Solid-State Circuits, 46, 5, pp. 1183-1197, (2011)

[2]

Beukema T., Sorna M., Selander K., A 6.4-Gb/s CMOS SerDes Core with feed-forward and decision-feedback equalization, IEEE J. Solid-State Circuits, 40, 12, pp. 2633-2645, (2005)

[3]

Dickson T.O., Bulzacchelli J.F., Friedman D.J., A 12 Gb/s 11 mW half-rate sampled 5-tap decision feedback equalizer with current integrating summers in 45 nm SOI CMOS technology, IEEE J. Solid-State Circuits, 44, 4, pp. 1298-1305, (2009)

[4]

Maeng M., Bien F., Hur Y., 0.18 μm CMOS Equalization Techniques for 10-Gb/s Fiber Optical Communication Link, IEEE Transactions on microwave theory and techniques, 53, 11, pp. 3509-3519, (2005)

[5]

Ju H., Zhou Y., Zhao J., A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link, Chinese Journal of Semiconductors, 32, 9, (2011)

[6]

Rothenberg B.C., Lewis S.H., A 20-M samples Switched-Capacitor Finite-Impulse-Response Filter Using a Transposed Structure, IEEE J. Solid-State Circuits, 30, 12, pp. 1350-1356, (1995)

[7]

Wang H., Lee J., A 21-Gbs 87-mW Transceiver With FFE/DFE Analog Equalizer in 65-nm CMOS Technology, IEEE J. Solid-State Circuits, 45, 4, pp. 909-920, (2010)

[8]

Gondi S., Razavi B., Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers, IEEE J. Solid-State Circuits, 42, 9, pp. 1999-2011, (2007)

[9]

Li L., Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18-μm CMOS, IEEE Transactions on Circults and Systems, 58, 3, pp. 441-450, (2011)

[10]

Seong C.-K., Rhim J., A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer with an Eye-Opening Monitor, IEEE Transactions on Circults and Systems, 59, 4, pp. 209-213, (2012)

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