High speed current domain CMOS D/A converter design

被引：0

作者：

Xu, Yang ^{[1
]}

Min, Hao ^{[1
]}

机构：

[1] Fudan Univ, Shanghai, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2000年 / 21卷 / 06期

关键词：

CMOS integrated circuits - Computer aided design - Electric currents - Errors;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A 10 bit 50 MS/s dual mode CMOS D/A converter fabricated with 1 μm CMOS technology was described. One mode is normal, another is power-save mode, in which a modified look-ahead circuit is designed to reduce power. The D/A converter was fabricated by using single-poly double-metal standard digital process. The integral nonlinearity error is less than 0.46 LSB. and the differential nonlinearity error is less than 0.03 LSB in the power-saving mode. The settling time to ±0.1% is less than 20 ns. The D/A converter has a single power supply of 5 V, and dissipates 250 mW at 50 MS/s when the input is 1023, while it dissipates 20 mW when the input is zero. The circuit chip size is 1.8 mm×2.4 mm.

引用

页码：597 / 601