High-level synthesis of timing and synchronization in I/O communication

被引：0

作者：

Meng, Han ^{[1
]}

Diao, Lan-Song ^{[1
]}

Liu, Ming-Ye ^{[1
]}

机构：

[1] Dept. of Comp. Sci. and Technol., Sch. of Info. Sci. and Eng., Beijing Inst. of Technol., Beijing 100081, China

来源：

Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | 2004年 / 24卷 / 02期

关键词：

Computer hardware description languages - Input output programs - Synchronization - Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The ways which express the timing and synchronization of VHDL and the meanings of consistency between pre- and post-synthesis simulation of VHDL source description are studied. For different meanings the method of synthesizing different statements is explained and realized. The ways of synthesis loop statement are different, if statement and case statement are different under different VHDL timing and constraints. Synthesis of other statements related to the loop is realized. The correctness and practicability of the method given is shown after running some typical examples.

引用

页码：125 / 128