Asymmetric trench SiC MOSFET with integrated channel accumulation diode for enhanced reverse conduction and switching characteristics

被引:0
|
作者
Gao, Sheng [1 ,2 ]
Zhang, Xianfeng [1 ]
Wang, Qi [1 ]
Yu, Shengqi [1 ]
Zuo, Yang [1 ,2 ]
Zhang, Hongsheng [1 ]
Huang, Yi [1 ]
机构
[1] Chongqing Univ Posts & Telecommun, Sch Optoelect Engn, Chongqing 400065, Peoples R China
[2] China Resources Microelect Chongqing Ltd, Chongqing 400030, Peoples R China
基金
中国国家自然科学基金;
关键词
SiC MOSFET; Reverse conduction; Low switching losses; Bipolar degradation; VOLTAGE; DIOMOS;
D O I
10.1016/j.mejo.2024.106436
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 mu C/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.
引用
收藏
页数:8
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