Hardware-Aware design for edge intelligence

被引：7
作者：
Gross W.J. [1 ]
Meyer B.H. [1 ]
Ardakani A. [1 ]
机构：
[1] Department of Electrical and Computer Engineering, McGill University, Montreal, QC
来源：
IEEE Open Journal of Circuits and Systems | 2021年 / 2卷
关键词：
Artificial intelligence; deep neural networks; hardware and systems; neural architecture search; quantization and pruning; stochastic computing; surveys and reviews;
D O I：
10.1109/OJCAS.2020.3047418
中图分类号：
学科分类号：
摘要：
With the rapid growth of the number of devices connected to the Internet, there is a trend to move intelligent processing of the generated data with deep neural networks (DNNs) from cloud servers to the network edge. Performing inference and training of DNNs in edge hardware is motivated by latency constraints, security and privacy concerns, and restricted network bandwidth. However, implementation of DNNs is challenging in resource-constrained edge devices. This article surveys recent advances in the efficient processing of DNNs, highlighting present research trends and future challenges. Specifically, we start by reviewing optimization methods for hardware-Aware deployment of DNNs. We then present some case studies of promising new directions towards low-complexity on-chip training. Finally, we discuss future challenges and their potential solutions for efficient deployment of DNNs at the edge. © 2020 IEEE.
引用
收藏
页码：113 / 127
页数：14
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