Design of a 10-Gb/s 0.18 μm CMOS multiplexer with the integrated clock generation circuit

Considering that, conventionally, a clock function block is not integrated with a multiplexer (MUX), which brings restrictions to MUX's integration and application, the research on integrating the clock circuit with a multiplexer was performed, and a 10-Gb/s half-rate 2:1 MUX with the integrated clock generation circuit was designed and fabricated in the SMIC 0.18 μm CMOS process. The whole circuit consists of a 5 Gb/s clock extraction circuit (CEC) and a 10 Gb/s half-rate 2:1 MUX. The CEC extracts a 5 GHz clock from one of two input data, and then provides the MUX with it. The CEC comprises a phase/frequency detector (PFD), a voltage/current converter (V/I), a loop filter (LF), and a voltage controlled oscillator (VCO). A Pottbäcker PFD can not only enlarge the pull-in range of the loop, but also tolerate up to ±45° phase error deviating from ideal inphase/quadrature (I/Q) clocks, so a 3-stage ring VCO can be employed. The measuremental results show that the circuit can work without any external component, reference clock, or manual tuning. The chip area is 670 μm×760 μm. Under a 1.8 V supply, it has the power consumption of 180 mW, in which, only 60% is used by the core blocks.