RED-SEA Project: Towards a new-generation European interconnect

被引:0
作者
Engracia Gomez, Maria [1 ]
Sahuquillo, Julio [1 ]
Biagioni, Andrea [2 ]
Chrysos, Nikos [3 ]
Berton, Damien [4 ]
Frezza, Ottorino [2 ]
Lo Cicero, Francesca [2 ]
Lonardo, Alessandro [2 ]
Martinelli, Michele [2 ]
Paolucci, Pier Stanislao [2 ]
Pastorelli, Elena [2 ]
Simula, Francesco [2 ]
Turisini, Matteo [2 ]
Vicini, Piero [2 ]
Ammendola, Roberto [2 ]
Chiarini, Carlotta [2 ]
De Luca, Chiara [5 ]
Capuani, Fabrizio [2 ]
Castello, Adrian [1 ]
Duro, Jose [1 ]
Stabile, Eugenio [1 ]
Quintana, Enrique [1 ]
Bernier-Bruna, Pascale [4 ]
Chen, Claire [4 ]
Lagadec, Pierre-Axel [4 ]
Pichon, Gregoire [4 ]
Walter, Etienne [4 ]
Katevenis, Manolis [3 ]
Bartzis, Sokratis [3 ]
Mousouros, Orestis [3 ]
Xirouchakis, Pantelis [3 ]
Mageiropoulos, Vangelis [3 ]
Gianioudis, Michalis [3 ]
Loukas, Harisis [3 ]
Ioannou, Aggelos [3 ]
Kallimanis, Nikos [3 ]
de la Rosa, Miguel Sanchez [6 ]
Gomez-Lopez, Gabriel [6 ]
Alfaro-Cortes, Francisco [6 ]
Sahuquillo, Jesus Escudero [6 ]
Garcia, Pedro Javier [6 ]
Quiles, Francisco J. [6 ]
Sanchez, Jose L. [6 ]
De Gassowski, Gaetan
Hautreaux, Matthieu [7 ]
Mathieu, Stephane [7 ]
Moreau, Gilles [7 ]
Perache, Marc [7 ]
Taboada, Hugo [7 ]
Hoefler, Torsten [8 ]
机构
[1] Univ Politecn Valencia, Valencia, Spain
[2] INFN, Sez Roma, Rome, Italy
[3] FORTH, Iraklion, Greece
[4] ATOS, Bezons, France
[5] Univ Roma La Sapienza, PhD Behav Neurosci, Rome, Italy
[6] Univ Castilla La Mancha, Ciudad Real, Spain
[7] CEA, Paris, France
[8] Swiss Fed Inst Technol, Zurich, Switzerland
[9] Exact Lab, Trieste, Italy
[10] Exapsys, Thessaloniki, Greece
[11] Extoll, Mannheim, Germany
[12] Julich Res Ctr, Julich, Germany
[13] ParTec AG, Munich, Germany
关键词
Interconnect; HPC; Congestion mechanism; Datacenter; Collective communication; Low-latency ethernet; QoS; SYSTEMS;
D O I
10.1016/j.micpro.2024.105102
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
RED-SEA is a H2020 EuroHPC project, whose main objective is to prepare a new-generation European Interconnect, capable of powering the EU Exascale systems to come, through an economically viable and technologically efficient interconnect, leveraging European interconnect technology (BXI) associated with standard and mature technology (Ethernet), previous EU-funded initiatives, as well as open standards and compatible APIs. To achieve this objective, the RED-SEA project is being carried out around four key pillars: (i) network architecture and workload requirements-interconnects co-design - aiming at optimizing the fit with the other EuroHPC projects and with the EPI processors; (ii) development of a high-performance, low-latency, seamless bridge with Ethernet; (iii) efficient network resource management, including congestion and Quality-of-Service; and (iv) end-to-end functions implemented at the network edges. This paper presents key achievements and results at the midterm of the project for each key pillar in the way to reach the final project objective. In this regard we can highlight: (i) The definition of the network requirements and architecture as well as a list of benchmarks and applications; (ii) In addition to initially planned IPs progress, BXI3 architecture has evolved to support natively Ethernet at low level, resulting in reduced complexity, with advantages in terms of cost optimization, and power consumption; (iii) The congestion characterization of target applications and proposals to reduce this congestion by the optimization of collective communication primitives, injection throttling and adaptive routing; and (iv) the low-latency high-message rate endpoint functions and their connection with new open technologies.
引用
收藏
页数:18
相关论文
共 37 条
[1]  
Abts D, 2010, CONF PROC INT SYMP C, P338, DOI 10.1145/1816038.1816004
[2]   QoS in InfiniBand subnetworks [J].
Alfaro, FJ ;
Sánchez, JL ;
Duato, J .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2004, 15 (09) :810-823
[3]  
Ammendola Roberto, 2013, 2013 IEEE International Symposium on Parallel and Distributed Processing, Workshops and PhD Forum (IPDPSW), P806, DOI 10.1109/IPDPSW.2013.128
[4]   APEnet+: a 3D Torus network optimized for GPU-based HPC Systems [J].
Ammendola, R. ;
Biagioni, A. ;
Frezza, O. ;
Lo Cicero, F. ;
Lonardo, A. ;
Paolucci, P. S. ;
Rossetti, D. ;
Simula, F. ;
Tosoratto, L. ;
Vicini, P. .
INTERNATIONAL CONFERENCE ON COMPUTING IN HIGH ENERGY AND NUCLEAR PHYSICS 2012 (CHEP2012), PTS 1-6, 2012, 396
[5]   An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators [J].
Andujar, Francisco J. ;
Villar, Juan A. ;
Alfaro, Francisco J. ;
Sanchez, Jose L. ;
Escudero-Sahuquillo, Jesus .
JOURNAL OF SUPERCOMPUTING, 2016, 72 (12) :4601-4628
[6]   RED-SEA: Network Solution for Exascale Architectures [J].
Biagioni, Andrea ;
Cretaro, Paolo ;
Frezza, Ottorino ;
Lo Cicero, Francesca ;
Lonardo, Alessandro ;
Martinelli, Michele ;
Paolucci, Pier Stanislao ;
Pastorelli, Elena ;
Simula, Francesco ;
Turisini, Matteo ;
Vicini, Piero ;
Ammendola, Roberto ;
Bernier-Bruna, Pascale ;
Chen, Claire ;
Derradji, Said ;
Guez, Stephane ;
Lagadec, Pierre-Axel ;
Pichon, Gregoire ;
Walter, Etienne ;
De Gassowski, Gaetan ;
Hautreaux, Matthieu ;
Mathieu, Stephane ;
Moreau, Gilles ;
Perache, Marc ;
Taboada, Hugo ;
Hoefler, Torsten ;
Schneider, Timo ;
Barnaba, Matteo ;
Brandino, Giuseppe Piero ;
De Giorgi, Francesco ;
Poggi, Matteo ;
Mavroidis, Iakovos ;
Papaefstathiou, Yannis ;
Tampouratzis, Nikolaos ;
Kalisch, Benjamin ;
Krackhardt, Ulrich ;
Nuessle, Mondrian ;
Xirouchakis, Pantelis ;
Mageiropoulos, Vangelis ;
Gianioudis, Michalis ;
Loukas, Harisis ;
Ioannou, Aggelos ;
Kallimanis, Nikos ;
Chrysos, Nikos ;
Katevenis, Manolis ;
Frings, Wolfang ;
Gottwald, Dominik ;
Guimaraes, Felime ;
Holicki, Max ;
Marx, Volker .
2022 25TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2022, :712-719
[7]   EuroEXA Custom Switch: an innovative FPGA-based system for extreme scale computing in Europe [J].
Biagioni, Andrea ;
Cretaro, Paolo ;
Frezza, Ottorino ;
Lo Cicero, Francesca ;
Lonardo, Alessandro ;
Paolucci, Pier Stanislao ;
Pontisso, Luca ;
Simula, Francesco ;
Vicini, Piero .
24TH INTERNATIONAL CONFERENCE ON COMPUTING IN HIGH ENERGY AND NUCLEAR PHYSICS (CHEP 2019), 2020, 245
[8]  
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
[9]   ENABLING SCALABLE HIGH-PERFORMANCE SYSTEMS WITH THE INTEL OMNI-PATH ARCHITECTURE [J].
Birrittella, Mark S. ;
Debbage, Mark ;
Huggahalli, Ram ;
Kunz, James ;
Lovett, Tom ;
Rimmer, Todd ;
Underwood, Keith D. ;
Zak, Robert C. .
IEEE MICRO, 2016, 36 (04) :38-47
[10]   Intel® Omni-Path Architecture Enabling Scalable, High Performance Fabrics [J].
Birrittella, Mark S. ;
Debbage, Mark ;
Huggahalli, Ram ;
Kunz, James ;
Lovett, Tom ;
Rimmer, Todd ;
Underwood, Keith D. ;
Zak, Robert C. .
PROCEEDINGS 2015 IEEE 23RD ANNUAL SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS - HOTI 2015, 2015, :1-9