A novel mesh-based hierarchical topology for network-on-chip

被引:0
作者
Kong, Feng [1 ]
Han, Guo-Dong [1 ]
Shen, Jian-Liang [1 ]
Jian, Gang [1 ]
机构
[1] National Digital Switching System Engineering and Technological R and D Center, Zhengzhou
来源
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2014年 / 36卷 / 10期
关键词
Hierarchical; Network diameter; Network-on-Chip (NoC); Traffic pattern;
D O I
10.3724/SP.J.1146.2013.01712
中图分类号
学科分类号
摘要
As the number of modules in System-on-Chip (SoC) increases, the topology is more likely to suffer from excessive end-to-end hop-counts, causing an increase of power consumption and area overhead. Concerning this issue, a novel Mesh-based Hierarchical topology called CHMesh is proposed, which is divided into two levels. The bottom level is interconnected with Mesh and divided into several regions, so as to guarantee communications of adjacent nodes, and the upper level employs intermediate nodes to promote the interconnection among different bottom routing regions with CMesh, so as to decrease the network diameter. Correspondingly, this article elaborates on a shortest-path CHXY routing algorithm, which has a low complexity and can realize deadlock avoidance. Performance analysis and experimental results demonstrate that, compared with traditional Mesh and Ref-Mesh, the CHMesh can increase the average throughput by about 60% and 10% respectively under non-uniform traffic patterns, presenting more advantages on large-scale NoC.
引用
收藏
页码:2536 / 2540
页数:4
相关论文
共 16 条
  • [1] Xiang D., Zhang Y., Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30, 1, pp. 135-147, (2011)
  • [2] Marculescu R., Ogras U.Y., Shiuan P.L., Et al., Outstanding research problem in NoC design: system, micro-architecture, and circuit perspectives, IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, 28, 1, pp. 3-21, (2009)
  • [3] Taylor M.B., Lee W., Miller J., Et al., Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams, Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 2-13, (2004)
  • [4] Feero B., Pande P., Performance evaluation for three-dimensional networks-on-chip, IEEE Computer Society Annual Symposium on VLSI, pp. 305-310, (2007)
  • [5] Chiu G.-M., The odd-even turn model for adaptive routing, IEEE Transactions on Parallel and Distributed Systems, 11, 7, pp. 729-738, (2000)
  • [6] Balfour J., Dally W.J., Design tradeoffs for tiled CMP on-chip networks, 20th Annual International Conference on Supercomputing, pp. 187-198, (2006)
  • [7] Loucif S., Performance evaluation of hierarchical-torus NoC, 27th International Conference on Advanced Information Networking and Applications Workshops, pp. 837-842, (2013)
  • [8] Kim J., Balfour J., Dally W., Flattened butterfly topology for on-chip networks, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 172-182, (2007)
  • [9] Zhu X.-J., Hu W.-W., Ma K., Et al., Xmesh: a mesh-like topology for network on chip, Journal of Software, 18, 9, pp. 2194-2204, (2007)
  • [10] Penaranda R., Gomez C., Et al., A new family of hybrid topologies for large-scale interconnection networks, 11th IEEE International Symposium on Network Computing and Applications, pp. 220-227, (2012)