A Low Jitter PLL Circuit using Time Amplifier

被引：0

作者：

Murakoshi Y. ^{[1
]}

Inagaki Y. ^{[2
]}

Matsuya Y. ^{[2
]}

机构：

[1] Electrical Engineering and Electronics Course, Graduate School of Science and Engineering, Aoyama Gakuin University, 5-10-1, Fuchinobe, Chuo-ku, Sagamihara, Kanagawa

[2] College of Science and Engineering, Aoyama Gakuin University, 5-10-1, Fuchinobe, Chuo-ku, Sagamihara, Kanagawa

来源：

IEEJ Transactions on Electronics, Information and Systems | 2021年 / 141卷 / 01期

关键词：

Nonlinear phase detector; Phase detector; Phase looked loop circuit; Time amplifier;

D O I：

10.1541/ieejeiss.141.25

中图分类号：

学科分类号：

摘要：

The frequency error and the phase noise decide on the performance of PLL. The phase noise of PLL is proportional to jitter. The jitter is degraded due to the dead time of the phase detector. In this paper, we proposed the time amplifier (TimeAMP) phase detector for reducing the dead time of the phase detector. The control pulse width of the charge pump switches is amplified from the time lag of input pulses by TimeAMP. We confirm by the transistor level simulation that the dead time is reduced to 1/100 and the lock time is reduced to 1/2. © 2021 The Institute of Electrical Engineers of Japan.

引用

页码：25 / 30

页数：5

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