High performance reconfigurable accelerator for deep convolutional neural networks

被引：0

作者：

Qiao R. ^{[1
,2
]}

Chen G. ^{[1
]}

Gong G. ^{[1
]}

Lu H. ^{[1
,2
,3
,4
]}

机构：

[1] Institute of Semiconductors, Chinese Academy of Sciences, Beijing

[2] University of the Chinese Academy of Sciences, Beijing

[3] Center for Excellence in Brain Science and Intelligence Technology, Chinese Academy of Sciences, Shanghai

[4] Semiconductor Neural Network Intelligent Perception and Computing Technology Beijing Key Lab, Beijing

来源：

Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2019年 / 46卷 / 03期

关键词：

Accelerator; Deep neural networks; High performance; Reconfigurable architecture; Very large scale integrated circuit;

D O I：

10.19665/j.issn1001-2400.2019.03.020

中图分类号：

学科分类号：

摘要：

In deep convolutional neural networks, the diversity of channel sizes and kernel sizes makes it difficult for existing accelerators to achieve efficient calculations. Therefore, based on the biological brain neuron mechanism, a deep convolutional neural network accelerator is proposed which can provide not only multiple clustering methods for brain-like neurons and link organization among brain-like neurons towards different channel sizes, but also three mapping methods for different convolution kernel sizes. The accelerator implements efficient reuse of local memory data, which greatly reduces the amount of data movement and improves the computing performance. Tested by the object classification network and object detection network, the accelerator's computational performance is 498.6 GOPS and 571.3 GOPS, respectively; the energy efficiency is 582.0 GOPS/W and 651.7 GOPS/W, respectively. © 2019, The Editorial Board of Journal of Xidian University. All right reserved.

引用

页码：130 / 139

页数：9

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