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Liu H., Datta S., Narayanan V., Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications, Proc. ISLPED, 2013, pp. 145-150, (2013)
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Dash S., Jena B., Mishra G.P., A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping, Superlattices Microstruct, 97, pp. 231-241, (2016)
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Das G.D., Dash S., Mishra G.P., Impact of source-pocket engineering on device performance of dielectric modulated tunnel FET, Superlattices Microstruct, 124, pp. 131-138, (2018)
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Madan J., Chaujar R., Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance, Superlat-tices Microstruct, 102, pp. 17-26, (2017)