Memristor-Based Material Implication Logic: Prelude to In-Memory Computing

被引：0
作者：
Mazady A. [2 ]
Anwar M. [1 ]
机构：
[1] Electrical and Computer Engineering Department, University of Connecticut, Storrs, 06269, CT
[2] Northrop Grumman Corporation, Baltimore, 212, MD
来源：
International Journal of High Speed Electronics and Systems | 2023年 / 32卷 / 2-4期
关键词：
IMP logic; in-memory computing; nanowire-based memristors;
D O I：
10.1142/S0129156423500210
中图分类号：
学科分类号：
摘要：
We report experimental demonstration of Material Implication (IMP) logic using ZnO nanowire-based memristors. The logic is demonstrated with a high-to-low resistance ratio of only five. This imposes much less stringent requirements on memristor performance that can enable IMP logic operation with lower bit error rates. Process independence on memristor and memristor-based IMP logic performance is demonstrated, and a more practical implementation of logic is made by relaxing the restriction imposed on the ranges of the values of on and off state resistances. IMP logic is validated up to a clock frequency of 100 KHz. © 2023 World Scientific Publishing Company.
引用
收藏
相关论文
共 32 条
  • [1] Di Ventra M., Pershin Y. V., Chua L. O., Circuit elements with memory: Memristors, memcapacitors, and meminductors, Proc. IEEE, 97, pp. 1717-1724, (2009)
  • [2] Borghetti J., Et al., A hybrid nanomemristor/transistor logic circuit capable of self-programming, Proc. Natl. Acad. Sci. USA, 106, pp. 1699-1703, (2009)
  • [3] Kvatinsky S., Et al., Memristor-based material implication (imply) logic: Design principles and methodologies, (2013)
  • [4] Shauly E. N., CMOS leakage and power reduction in transistors and circuits: Process and layout considerations, J. Low Power Electron. Appl, 2, pp. 1-29, (2012)
  • [5] Houssa M., High k gate dielectrics, (2003)
  • [6] Yeap G. C., Krishnan S., Lin M., Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-k gate dielectrics, Electron. Lett, 34, pp. 1150-1152, (1998)
  • [7] Wu C., Et al., High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme, 2010 IEEE International Electron Devices Meeting (IEDM), (2010)
  • [8] Collaert N., Et al., Multi-gate devices for the 32nm technology node and beyond, Solid-State Electron, 52, pp. 1291-1296, (2008)
  • [9] Manoj C., Nagpal M., Varghese D., Ramgopal Rao V., Device design and optimization considerations for bulk FinFETs, IEEE Trans. Electron Devices, 55, pp. 609-615, (2008)
  • [10] Gaynor B. D., Hassoun S., Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design, IEEE Trans. Electron Devices, 61, pp. 2738-2744, (2014)
1234