Design of a low-power 12-bit 1msps sar analog-to-digital converter

In this paper, a low-power 12-bit 1MSps Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) is proposed to increase the integration degree. The proposed circuit is designed using the 1Poly-6Metal 0.13 μm CMOS process, and operates at a supply voltage of 1.2 V. A pre-amplifier is incorporated to amplify both comparator and buffer, and offer flexible signal processing and good performance. The signal processing stage is compared to conventional circuits, so that fine signals can be captured for optimization. The proposed ADC showed very low power consumption (0.654 mW), good Figure of Merit (FOM) (0.98 fJ/conversion) and smaller die area (0.106 mm2) compared with conventional results. This circuit also showed excellent Effective Number of Bits (ENOB) and high Signal-to-Noise Distortion Ratio (SNDR), 72.19 dB and 11.69 bits respectively. © ICROS 2021.