Hardware implementation of approximate multipliers for signal processing applications

被引：0
作者：
Konguvel E. [1 ]
Hariharan I. [2 ]
Sujatha R. [2 ]
Kannan M. [3 ]
机构：
[1] School of Electronics Engineering (SENSE), Vellore Institute of Technology (VIT), Vellore
[2] School of Electronics Engineering (SENSE), Vellore Institute of Technology (VIT), Chennai
[3] Department of Electronics Engineering, Anna University, MIT Campus, Chennai
来源：
International Journal of Wireless and Mobile Computing | 2022年 / 23卷 / 3-4期
关键词：
adders; approximate computing; error analysis; hardware; multipliers; VLSI design;
D O I：
10.1504/ijwmc.2022.127595
中图分类号：
学科分类号：
摘要：
Multiplication is a complex and substantial arithmetic task involved in signal processing applications. The hardware complexity of the multiplier is always high when compared with any other arithmetic operation. Approximate multiplication is a common operation used in many signal processing applications for improved performance and low-power computation. The proposed approximate multiplier design is based on the approximate 4-2 compressor and self-error recovery technique. A small modification of the truth table entries in the approximate 4-2 compressor shows performance improvement at a small cost of accuracy. The designed multiplier promises to have improved performance when compared with the earlier approximate designs. The computational errors arising because of this multiplication approximation can be considered as trade-off for the significant gains in power and area. Copyright © 2022 Inderscience Enterprises Ltd.
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页码：302 / 309
页数：7
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