Hardware implementation of approximate multipliers for signal processing applications

被引：0

作者：

Konguvel E. ^{[1
]}

Hariharan I. ^{[2
]}

Sujatha R. ^{[2
]}

Kannan M. ^{[3
]}

机构：

[1] School of Electronics Engineering (SENSE), Vellore Institute of Technology (VIT), Vellore

[2] School of Electronics Engineering (SENSE), Vellore Institute of Technology (VIT), Chennai

[3] Department of Electronics Engineering, Anna University, MIT Campus, Chennai

来源：

International Journal of Wireless and Mobile Computing | 2022年 / 23卷 / 3-4期

关键词：

adders; approximate computing; error analysis; hardware; multipliers; VLSI design;

D O I：

10.1504/ijwmc.2022.127595

中图分类号：

学科分类号：

摘要：

Multiplication is a complex and substantial arithmetic task involved in signal processing applications. The hardware complexity of the multiplier is always high when compared with any other arithmetic operation. Approximate multiplication is a common operation used in many signal processing applications for improved performance and low-power computation. The proposed approximate multiplier design is based on the approximate 4-2 compressor and self-error recovery technique. A small modification of the truth table entries in the approximate 4-2 compressor shows performance improvement at a small cost of accuracy. The designed multiplier promises to have improved performance when compared with the earlier approximate designs. The computational errors arising because of this multiplication approximation can be considered as trade-off for the significant gains in power and area. Copyright © 2022 Inderscience Enterprises Ltd.

引用

页码：302 / 309

页数：7

共 24 条

[1]

Chang C.H., Gu J., Zhang M., Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, 51, 10, pp. 1985-1997, (2004)

[2]

Cui Z., Zhang J., Wang Y., Cao Y., Cai X., Zhang W., Chen J., A pigeon-inspired optimization algorithm for many-objective optimization problems, Science China Information Sciences, 62, 7, pp. 1-3, (2019)

[3]

Du J., Chen K., Yin P., Yan C., Liu W., Design of an approximate FFT processor based on approximate complex multipliers, Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 308-313, (2021)

[4]

Edavoor P.J., Raveendran S., Rahulkar A.D., Approximate multiplier design using novel dual-stage 4: 2 compressors, IEEE Access, 8, pp. 48337-48351, (2020)

[5]

Elango K., Muniandi K., VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications, Annals of Telecommunications, 75, 5, pp. 215-227, (2020)

[6]

Esposito D., Strollo A.G.M., Napoli E., De Caro D., Petra N., Approximate multipliers based on new approximate compressors, IEEE Transactions on Circuits and Systems I: Regular Papers, 65, 12, pp. 4169-4182, (2018)

[7]

Ghosh A., Konguvel E., ATM services on EMU8086 for the technologically impaired people, Proceedings of the IEEE International Conference on Computer Communication and Informatics, (2022)

[8]

Ha M., Lee S., Multipliers with approximate 4-2 compressors and error recovery modules, IEEE Embedded Systems Letters, 10, 1, pp. 6-9, (2018)

[9]

Han J., Orshansky M., Approximate computing: an emerging paradigm for energy-efficient design, Proceedings of 18th IEEE European Test Symposium, pp. 1-6, (2013)

[10]

Hashemi S., Bahar R., Reda S., DRUM: a dynamic range unbiased multiplier for approximate applications, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 418-425, (2015)

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