Analyzing single event upset on Kintex-7 Field-Programmable-Gate-Array with random fault injection method

被引:3
作者
Wang Z. [1 ]
Chen W. [1 ,2 ]
Yao Z. [2 ]
Zhang F. [2 ]
Luo Y. [2 ]
Tang X. [1 ]
Peng C. [1 ]
Ding L. [2 ]
Guo X. [2 ]
机构
[1] Department of Nuclear Science and Technology, Nanjing University of Aeronautics and Astronautics, Nanjing
[2] State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, Xi'an
基金
中国国家自然科学基金;
关键词
Fault injection; FPGA; Random injection; Triple module redundancy;
D O I
10.1016/j.nima.2020.163866
中图分类号
学科分类号
摘要
In this paper, the bitstream of 28 nm field-programmable-gate-array was resolved. The relationship between the frame address and the resource was obtained. The fault injection platform was designed based on the information of the bitstream which obtained by partial reconfiguration. With this fault injection platform, the equivalence of the global fault and random fault injections was verified. Also, the sensitivities of different circuits were tested by random fault injection. The reinforcement effect of the triple module redundancy for sensitive resources in 28 nm FPGA was also be tested. © 2020
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  • [1] Ceschia M., Violante M., Reorda M.S., Paccagnella A., Bernardi P., Rebaudengo M., Candelori A., Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 50, pp. 2088-2094, (2003)
  • [2] Quinn H., Morgan K., Graham P., Krone J., Caffrey M., A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5, 2007 9th European Conference on Radiation and its Effects on Components and Systems, pp. 1-8, (2007)
  • [3] Sterpone L., Violante M., A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 52, pp. 2217-2223, (2005)
  • [4] Kretzschmar U., Astarloa A., Jimenez J., Garay M., Del Ser J., Compact and fast fault injection system for robustness measurements on SRAM-based FPGAs, IEEE Trans. Ind. Electron., 61, pp. 2493-2503, (2014)
  • [5] Sterpone L., Violante M., A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 54, pp. 965-970, (2007)
  • [6] Zhang R., Xiao L., Li J., Cao X., Qi C., Li J., Wang M., A fast fault injection platform of multiple SEUs for SRAM-based FPGAs, elsevier microelectron, Reliab., 82, pp. 147-152, (2018)
  • [7] Di Carlo S., Prinetto P., Rolfo D., Trotta P., A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 159-164, (2014)
  • [8] Tarrillo J., Tonfat J., Tambara L., Reis R., Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments, 2015 16th Latin-American Test Symposium (LATS), pp. 1-6, (2015)
  • [9] Ullah A., Reviriego P., Maestro J.A., An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs, IEEE Trans. Nucl. Sci., 65, pp. 989-996, (2018)
  • [10] Violante M., Sterpone L., Ceschia M., Bortolato D., Bernardi P., Reorda M.S., Paccagnella A., Simulation-based analysis of SEU effects in SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 51, pp. 3354-3359, (2004)