共 16 条
- [1] Ceschia M., Violante M., Reorda M.S., Paccagnella A., Bernardi P., Rebaudengo M., Candelori A., Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 50, pp. 2088-2094, (2003)
- [2] Quinn H., Morgan K., Graham P., Krone J., Caffrey M., A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5, 2007 9th European Conference on Radiation and its Effects on Components and Systems, pp. 1-8, (2007)
- [3] Sterpone L., Violante M., A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 52, pp. 2217-2223, (2005)
- [4] Kretzschmar U., Astarloa A., Jimenez J., Garay M., Del Ser J., Compact and fast fault injection system for robustness measurements on SRAM-based FPGAs, IEEE Trans. Ind. Electron., 61, pp. 2493-2503, (2014)
- [5] Sterpone L., Violante M., A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 54, pp. 965-970, (2007)
- [6] Zhang R., Xiao L., Li J., Cao X., Qi C., Li J., Wang M., A fast fault injection platform of multiple SEUs for SRAM-based FPGAs, elsevier microelectron, Reliab., 82, pp. 147-152, (2018)
- [7] Di Carlo S., Prinetto P., Rolfo D., Trotta P., A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 159-164, (2014)
- [8] Tarrillo J., Tonfat J., Tambara L., Reis R., Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments, 2015 16th Latin-American Test Symposium (LATS), pp. 1-6, (2015)
- [9] Ullah A., Reviriego P., Maestro J.A., An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs, IEEE Trans. Nucl. Sci., 65, pp. 989-996, (2018)
- [10] Violante M., Sterpone L., Ceschia M., Bortolato D., Bernardi P., Reorda M.S., Paccagnella A., Simulation-based analysis of SEU effects in SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 51, pp. 3354-3359, (2004)