共 50 条
[21]
Optimization analysis of thermal network layout
[J].
HEAT TRANSFER SCIENCE AND TECHNOLOGY 2000,
2000,
:837-842
[22]
Interconnect Test for 3D Stacked Memory-on-Logic
[J].
2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE),
2014,
[24]
3D integrated circuit layout visualization using VRML
[J].
PROCEEDINGS OF THE 1999 INTERNATIONAL CONFERENCE ON WEB-BASED MODELING AND SIMULATION,
1999, 31 (03)
:177-181
[26]
Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level
[J].
DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII,
2019, 10962