In the Pursuit of the Optimal Accuracy-Speed-Power Analog-to-Digital Converter Architecture: A mathematical framework

被引：1
作者：
Ramkaj A. [1 ]
Pelgrom M.J.M. [2 ]
Steyaert M.S.J. [3 ]
Tavernier F. [4 ]
机构：
[1] Stanford University, Stanford, CA
[2] University of California, Los Angeles, CA
[3] KU Leuven, Leuven
来源：
IEEE Solid-State Circuits Magazine | 2022年 / 14卷 / 01期
关键词：
Product design - Analog to digital conversion;
D O I：
10.1109/MSSC.2021.3128310
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
The everlasting challenge in the design of every analog-to-digital converter (ADC) lies in maximizing the accuracy·speed÷power product by pushing all metrics toward their desired directions. To this end, tremendous progress has been made in advancing ADC performance both circuit- and architecture-wise. These advances have been captured by means of comparing experimental data points in surveys, with [1] being the most noteworthy. However, such comparisons give an ill-defined view since the data points correspond to different architectures that were optimized under different constraints and implemented in different process nodes. This provides little insight on architectural limits and makes a direct comparison under similar assumptions nontrivial. © 2009-2012 IEEE.
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收藏
页码：45 / 53
页数：8
相关论文
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