Design and Optimization of Multi-Modulus-Divider for K-Band Fractional-N Frequency Synthesizer

被引：0
|
作者：
Wang Z.-C. [1 ]
Wu Z.-B. [1 ]
Qi Q.-W. [1 ]
Wang X.-H. [1 ]
机构：
[1] Beijing Silicon SoC Engineering Research Center, School of Information and Electronics, Beijing Institute of Technology, Beijing
来源：
Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | 2019年 / 39卷 / 11期
关键词：
Fractional-N frequency synthesizer; Multi-modulus-divider; Retime circuit technique;
D O I：
10.15918/j.tbit1001-0645.2017.329
中图分类号：
学科分类号：
摘要：
A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively. © 2019, Editorial Department of Transaction of Beijing Institute of Technology. All right reserved.
引用
收藏
页码：1187 / 1191
页数：4
相关论文
共 12 条
  • [1] Wang J., Li J., Wu S., Tracking error analysis of FLL-assisted-PLL, Transactions of Beijing Institute of Technology, 7, pp. 838-843, (2011)
  • [2] Huang C., Ren L., Mao E., Et al., An X-band broadband fast settling frequency synthesizer, Transactions of Beijing Institute of Technology, 4, pp. 467-471, (2011)
  • [3] Yang Z., Analysis of phase noise in frequency synthesizer and fully-differential charge pump design, (2007)
  • [4] Zhang G., Design of CMOS Integrated Phase-Locked Loops, (2013)
  • [5] Luo C., Wu H.E., Nian C., A 77-GHz CMOS FMCW frequency synthesizer with reconfigurable chirps, IEEE Transactions on Microwave Theory and Techniques, 7, 61, pp. 2641-2647, (2013)
  • [6] Rhee W., Song B., A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ Σ modulator, IEEE Journal of Solid-State Circuits, 10, 35, pp. 1453-1460, (2000)
  • [7] Ferriss M., Sadhu B., Rylyakov A., Et al., 1A 12-to-26 GHz fractional-N PLL with dual continuous tuning LCD/VCOs, IEEE International Solid-State Circuits Conference, pp. 196-198, (2016)
  • [8] Ferriss M., Sadhu B., Rylyakov A., Et al., A 13.1-to-28 GHz fractional-N PLL in 32 nm SOI CMOS with a ΔΣ noise-cancellation scheme, IEEE International Solid-State Circuits Conference, pp. 1-3, (2015)
  • [9] Gyuseob J., Kim W., Park J., Et al., A 0.015 mm<sup>2</sup> inductorless 32 GHz clock generator with wide frequency tuning range in 28 nm CMOS technology, IEEE Transactions on Circuits & Systems II Express Briefs, 64, 6, pp. 1-5, (2015)
  • [10] Ferriss M., Plouchart J.-O., Natarajan A., Et al., An integral path self-calibration scheme for a dual-loop PLL, IEEE Journal of Solid-State Circuits, 4, 48, pp. 996-1008, (2013)
12