Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

被引：0

作者：

Kitamura T. ^{[1
]}

Hisakado T. ^{[1
]}

Wada O. ^{[1
]}

Islam M. ^{[1
]}

机构：

[1] Department of Electrical Engineering, Graduate School of Engineering, Kyoto University, Kyoto

来源：

IPSJ Transactions on System LSI Design Methodology | 2024年 / 17卷

基金：

日本学术振兴会;

关键词：

distribution tuning; flash ADC; Johnson distribution; normal distribution; offset voltage; on-chip calibration; order statistics;

D O I：

10.2197/ipsjtsldm.17.36

中图分类号：

学科分类号：

摘要：

Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65 nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption. © 2024 Information Processing Society of Japan.

引用

页码：36 / 43

页数：7

共 17 条

[1]

Weaver S., Hershberg B., Kurahashi P., Knierim D., Moon U.K., Stochastic flash analog-to-digital conversion, IEEE Trans. Circuits Syst. I: Regul. Pap, 57, 11, pp. 2825-2833, (2010)

[2]

Fahmy A., Liu J., Kim T., Maghari N., An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells, IEEE Trans. Circuits Syst. II: Express Briefs, 62, 8, pp. 731-735, (2015)

[3]

Jeon M.K., Yoo W.J., Kim C.G., Yoo C., A stochastic flash analog-to-digital converter linearized by reference swapping, IEEE Access, 5, pp. 23046-23051, (2017)

[4]

Uto S., Ohhata K., Stochastic subranging ADC using variable comparator offset technique, IEEE Int. Symp. Radio-Frequency Integr. Technol. RFIT, 2020, pp. 232-234, (2020)

[5]

Van der Plas G., Decoutere S., Donnay S., A 0.16 pJ/conversionstep 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process, IEEE Int. Solid-State Circuits Conf, pp. 566-567, (2006)

[6]

Sundstrom T., Alvandpour A., Utilizing process variations for reference generation in a flash ADC, IEEE Trans. Circuits Syst. II: Express Briefs, 56, 5, pp. 364-368, (2009)

[7]

Chen V.H., Pileggi L., An 8.5 mW 5 GS/s 6b flash ADC with dynamic offset calibration in 32 nm CMOS SOI, IEEE Symposium on VLSI Circuits, pp. 264-265, (2013)

[8]

Shu Y.S., A 6b 3 GS/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators, Symposium on VLSI Circuits (VLSIC), pp. 26-27, (2012)

[9]

Kitamura T., Islam M., Hisakado T., Wada O., Flash ADC utilizing offset voltage variation with order statistics based comparator selection, Proc. Int. Symp. Qual. Electron. Des. ISQED, pp. 103-108, (2021)

[10]

Kitamura T., Islam M., Hisakado T., Wada O., Order statistics based low-power flash ADC with on-chip comparator selection, IEICE Trans. Fundam. Electron. Commun. Comput. Sci, E105-A, 11, pp. 1450-1457, (2022)

← 1 2 →