Acceleration platform for face detection and recognition based on field-programmable gate array

被引：0
|
作者：
Zhou Y. [1 ,2 ]
Yang S. [1 ,2 ]
Li D.-L. [1 ,2 ]
Wu C.-G. [1 ,2 ]
Wang Y. [1 ,2 ]
Wang K.-P. [1 ,2 ]
机构：
[1] College of Computer Science and Technology, Jilin University, Changchun
[2] Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education, Jilin University, Changchun
来源：
Jilin Daxue Xuebao (Gongxueban)/Journal of Jilin University (Engineering and Technology Edition) | 2019年 / 49卷 / 06期
关键词：
Algorithm hardware; Computer application; Convolution neural network; Face detection; Face recognition; Field programmable gate array(FPGA) algorithm;
D O I：
10.13229/j.cnki.jdxbgxb20180480
中图分类号：
学科分类号：
摘要：
A heterogeneous computing technique based on Field-Programmable Gate Array (FPGA) is proposed in this paper. The Viola-Jones face detection algorithm is accelerated based on concurrent and pipelining methods to improve data throughput and increase the parallelism of cascaded classifiers and convolution neural network is accelerated by concurrent convolution and pipelined feature maps. The experimental results show that the hardware platform achieves a speedup of 2.9 times compared with the software platform. © 2019, Jilin University Press. All right reserved.
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页码：2051 / 2057
页数：6
相关论文
共 14 条
  • [1] Viola P., Jones M.J., Rapid object detection using a boosted cascade of simple features, IEEE Computer Society Conference on Computer Vision & Pattern Recognition, pp. 511-518, (2001)
  • [2] Zhao W., Chellappa R., Phillips P.J., Et al., Face recognition: a literature survey, ACM Computing Surveys, 35, 4, pp. 399-458, (2003)
  • [3] Tanaka Y., Maejima H., Loop optimization method for recurrences on a processor with instruction level parallelism, IPSJ Journal, 37, pp. 1657-1665, (1996)
  • [4] Brodtkorb A.R., Hagen T.R., A comparison of three commodity-level parallel architectures: multi-core CPU, Cell BE and GPU, LNCS, 5862, pp. 70-80, (2010)
  • [5] Matell M.S., Bateson M., Meck W.H., Et al., Single-trials analyses demonstrate that increases in clock speed contribute to the methamphetamine-induced horizontal shifts in peak-interval timing functions, Psychopharmacology, 188, 2, pp. 201-212, (2006)
  • [6] Che S., Li J., Sheaffer J.W., Et al., Accelerating compute-intensive applications with GPUs and FPGAs, 2008 Symposium on Application Specific Processors, pp. 101-107, (2008)
  • [7] Zhou Y.-T., Wang W., Huang X.-M., FPGA design for PCANet deep learning network, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, (2015)
  • [8] Jin S., Cho J., Pham X.D., Et al., FPGA design and implementation of a real-time stereo vision system, IEEE Transactions on Circuits & Systems for Video Technology, 20, 1, pp. 15-26, (2010)
  • [9] Neshatpour K., Malik M., Ghodrat M.A., Et al., Accelerating big data analytics using fpgas, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, (2015)
  • [10] Srivastava N., Dai S., Manohar R., Et al., Accelerating face detection on programmable SoC using C-based synthesis, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 195-200, (2017)
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