DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

被引：1

作者：

Yahara M. ^{[1
]}

Fujimoto K. ^{[2
]}

Nishiguchi D. ^{[3
]}

Harada Y. ^{[4
]}

Fukuhara M. ^{[3
]}

机构：

[1] Department of Medical Care and Welfare Engineering, Tokai University, 9-1-1, Toroku, Higashi-ku, Kumamoto-shi, Kumamoto

[2] Department of Electronics and Intelligent Systems Engineering, Tokai University, 9-1-1, Toroku, Higashi-ku, Kumamoto-shi, Kumamoto

[3] Graduate School of Information and Telecommunication Engineering, Tokai University, 2-3-23, Takanawa, Minato-ku, Tokyo

[4] Department of Electrical and Electronic Engineering, National Institute of Technology, Kurume College, 1-1-1, Komorino, Kurume-shi, Fukuoka

来源：

International Journal of Innovative Computing, Information and Control | 2022年 / 18卷 / 06期

关键词：

Divider; Frequency error; Frequency-locked loop; Multi-phase clock; PLL;

D O I：

10.24507/ijicic.18.06.1979

中图分类号：

学科分类号：

摘要：

An all-digital frequency-locked loop (DFLL) using a multi-phase clock-based 1 + 1/k divider has been proposed. This circuit can reduce the jitter of the output signal extremely small. However, it has the problem of a narrow lock-in range. In this paper, we propose a DFLL with a wide frequency lock-in range and low frequency error using the m + n/k divider based on a multi-phase clock. The proposed DFLL can realize an extremely wide frequency lock-in range compared to the conventional DFLL using a multi-phase clock. Also, the frequency detection error between input and output signals can be kept within one phase difference of the multi-phase clock. As a result, the steady-state frequency error of the output signal is also within one phase difference of the multi-phase clock. These characteristics were confirmed by simulation using Verilog-HDL, a hardware description language. © 2022, ICIC International. All rights reserved.

引用

页码：1979 / 1988

页数：9

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