Development of a RISC-V-conform fused multiply-add floating-point unit

Despite the fact that the open-source community around the RISC-V instruction set archi- tecture is growing rapidly, there is still no high-speed open-source hardware implementation of the IEEE 754-2008 oating-point standard available. We designed a Fused Multiply-Add Floating- Point Unit compatible with the RISC-V ISA in SystemVerilog, which enables us to conduct de- tailed optimizations where necessary. The design has been verified with the industry standard simulation-based Universal Verification Methodology using the Specman e Hardware Verification Language. The most challenging part of the verification is the reference model, for which we in- tegrated the Floating-Point Unit of an existing Intel processor using the Function Level Interface provided by Specman e. With the use of Intel's Floating-Point Unit we have a "known good" and fast reference model. The Back-End ow was done with Global Foundries' 22 nm Fully-Depleted Silicon-On-Insulator (GF22FDX) process using Cadence tools. We reached 1.8 GHz over PVT corners with a 0.8 V forward body bias, but there is still a large potential for further RTL opti- mization. A power analysis was conducted with stimuli generated by the verification environment and resulted in 212 mW. © The Authors 2019.