All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

被引：1

作者：

Ta V.-T. ^{[1
]}

Hoang V.-P. ^{[1
]}

Tran X.N. ^{[1
]}

机构：

[1] Le Quy Don Technical University, Hanoi

来源：

EAI Endorsed Transactions on Industrial Networks and Intelligent Systems | 2019年 / 6卷 / 21期

关键词：

all-digital background calibration; channel mismatches; Time-interleaved analog-to-digital converter;

D O I：

10.4108/eai.24-10-2019.160983

中图分类号：

学科分类号：

摘要：

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the sub-ADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations. © 2019. Van-Thanh Ta et al., licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/3.0/), which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.

引用

共 21 条

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