Towards a Formal Treatment of Logic Locking

被引:0
|
作者
Beerel P. [1 ]
Georgiou M. [2 ]
Hamlin B. [2 ]
Malozemoff A.J. [2 ]
Nuzzo P. [1 ]
机构
[1] University of Southern California, Los Angeles, CA
[2] Galois, Inc, Portland, OR
来源
IACR Transactions on Cryptographic Hardware and Embedded Systems | 2022年 / 2022卷 / 02期
关键词
Logic Locking; Security Definitions;
D O I
10.46586/tches.v2022.i2.92-114
中图分类号
学科分类号
摘要
Logic locking aims to protect the intellectual property of a circuit from a fabricator by modifying the original logic of the circuit into a new “locked” circuit such that an entity without the key should not be able to learn anything about the original circuit. While logic locking provides a promising solution to outsourcing the fabrication of chips, unfortunately, several of the proposed logic locking systems have been broken. The lack of established secure techniques stems in part from the absence of a rigorous treatment toward a notion of security for logic locking, and the disconnection between practice and formalisms. We seek to address this gap by introducing formal definitions to capture the desired security of logic locking schemes. In doing so, we investigate prior definitional efforts in this space, and show that these notions either incorrectly model the desired security goals or fail to capture a natural “compositional” property that would be desirable in a logic locking system. Finally we move to constructions. First, we show that universal circuits satisfy our security notions. Second, we show that, in order to do better than universal circuits, cryptographic assumptions are necessary. © 2022, Ruhr-University of Bochum. All rights reserved.
引用
收藏
页码:92 / 114
页数:22
相关论文
共 50 条
  • [41] SAT Based Partial Attack on Compound Logic Locking
    John, Melbin
    Hoda, Aadil
    Chouksey, Ramanuj
    Karfa, Chandan
    PROCEEDINGS OF THE 2020 ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST), 2020,
  • [42] Generalized SAT-Attack-Resistant Logic Locking
    Zhou, Jingbo
    Zhang, Xinmiao
    IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 2021, 16 : 2581 - 2592
  • [43] Special Session: Novel Attacks on Logic-Locking
    Jain, Ayush
    Guin, Ujjwal
    Rahman, M. Tanjidur
    Asadizanjani, Navid
    Duvalsaint, Danielle
    Blanton, R. D. Shawn
    2020 IEEE 38TH VLSI TEST SYMPOSIUM (VTS 2020), 2020,
  • [44] Logic Locking: A Survey of Proposed Methods and Evaluation Metrics
    Dupuis, Sophie
    Flottes, Marie-Lise
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2019, 35 (03): : 273 - 291
  • [45] HOLL: Program Synthesis for Higher Order Logic Locking
    Takhar, Gourav
    Karri, Ramesh
    Pilato, Christian
    Roy, Subhajit
    TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, TACAS 2022, PT I, 2022, 13243 : 3 - 24
  • [46] Limes: Logic locking on interleaved memory for enhanced security
    Sai Prasanna A.
    Tejeswini J.
    Mohankumar N.
    Lecture Notes on Data Engineering and Communications Technologies, 2021, 66 : 613 - 626
  • [47] StateLock: State Transition Based Logic Locking for Sequential Circuits
    Kasarabada, Yasaswy
    Vemuri, Ranga
    2020 33RD INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2020 19TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2020, : 171 - 176
  • [48] Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures
    Mustafa, Yerzhan
    Jabbari, Tahereh
    Kose, Selcuk
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (03)
  • [49] Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
    Sisejkovic, Dominik
    Reimann, Lennart M.
    Moussavi, Elmira
    Merchant, Farhad
    Leupers, Rainer
    PROCEEDINGS OF THE 2021 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2021, : 7 - 12
  • [50] Discerning Limitations of GNN-based Attacks on Logic Locking
    Darjani, Armin
    Kavand, Nima
    Rai, Shubham
    Kumar, Akash
    2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC, 2023,