High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

被引：0

作者：

Siva Singh S.K.B. ^{[1
]}

Karthikeyan K.V. ^{[1
]}

机构：

[1] Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Tamil Nadu, Chennai

来源：

International Journal of High Performance Systems Architecture | 2023年 / 11卷 / 03期

关键词：

D-flip flop; decoder; delay line output duty cycle; digital pulse width modulator; DPWM; linearity; reversible synchronous sequential counter; synchronous phase shifted circuit; synchronous reversible counter; time resolution;

D O I：

10.1504/IJHPSA.2023.130225

中图分类号：

学科分类号：

摘要：

Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE. Copyright © 2023 Inderscience Enterprises Ltd.

引用

页码：148 / 155

页数：7

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