Low power architecture of 8bit-9bit encoder and 9bit-8bit decoder using clock gating scheme

Clock gating is an efficient technique for reducing power consumption in digital design. It saves more power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. The proposed architecture used to control the encoder and decoder modules. In this paper a clock gated 8bit-9bit encoder and 9bit-8bit decoder design was executed. The proposed design with gated clock using negative latch clock gating improves power consumption without degrading the design performance. The suggested scheme was achieved 32.18% reduction in power consumption. Encoder and decoder module was executed by using Application-Specific Integrated Circuit (ASIC) design methodology. In order to execute design architecture, 130 nm technology libraries were used for ASIC implementation. The construction of coding and decoding process has been created using Verilog HDL language to cover all the functions. In addition, the simulations are carried out by using ModelSim-Altera 10.3c (Quartus II 14.1) in 130 nm technology. ©2019 by Begell House, Inc.