A reconfigurable 4T2R ReRAM computing in-memory macro for efficient edge applications

被引：19

作者：

Chen Y. ^{[1
]}

Lu L. ^{[1
]}

Kim B. ^{[2
]}

Kim T.T.-H. ^{[1
]}

机构：

[1] School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

[2] Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, 93106, CA

来源：

IEEE Open Journal of Circuits and Systems | 2021年 / 2卷

关键词：

computing in-memory (CIM); reconfigurable architecture; Resistive random access memory (ReRAM); ternary content addressable memory (TCAM);

D O I：

10.1109/OJCAS.2020.3042550

中图分类号：

学科分类号：

摘要：

Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures. We propose a reconfigurable ReRAM architecture using a novel 4T2R bit-cell that supports non-volatile storage and two types of CIM operations: i) ternary content addressable memory (TCAM) and ii) in-memory dot product (IM-DP) for neural networks. The proposed 4T2R cell occupies a smaller area than prior SRAM-based CIM bit-cells. A 128 × 128 ReRAM macro is designed in 40nm CMOS technology. For TCAM operations, it allows a search word-length of 128 bits. For IM-DP operations, it can compute parallel dot products using binary inputs and ternary weights. The simulated search delay for TCAM operation is 0.92 ns at VDD = 0.9 V and the simulated energy efficiency for IM-DP operation is 223.6 TOPS/W at VDD = 0.7 V. Monte-Carlo simulations show a standard deviation of 4.9% in accumulate operation for IM-DP which corresponds to a classification accuracy of 95.7% on the MNIST dataset and 81.7% on the CIFAR-10 dataset. © 2020 IEEE.

引用

页码：210 / 222

页数：12

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