Efficient Memory Circuits Yield Analysis and Optimization Framework via Meta-Learning

被引:0
作者
Wang, Ziqi [1 ]
Pang, Liang [1 ]
Shi, Xiao [1 ,2 ]
Shi, Longxing [1 ]
机构
[1] Natl Ctr Technol Innovat EDA, Nanjing, Peoples R China
[2] Southeast Univ, Sch Comp Sci & Engn, Nanjing 210018, Peoples R China
基金
中国国家自然科学基金;
关键词
Integrated circuit modeling; Optimization; Task analysis; Training; Analytical models; Yield estimation; Metalearning; Yield optimization; meta-learning; baseline model; memory circuits; SRAM; ANALOG;
D O I
10.1109/TCSII.2024.3376388
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Yield optimization is a computationally intensive process that requires repeated yield estimation. In this brief, we propose a yield-driven optimization process based on meta-model yield analysis for memory circuits. Choosing the Artificial Neural Network (ANN) as surrogate model, we propose a model generation strategy to learn better initialization of network parameters via meta-learning. We improve the Differential Evolution (DE) algorithm to guide the optimization process and fine-tune the yield surrogate model in each iteration with limited simulation overheads. The experimental results validated on the memory circuits show that the proposed method can achieve final results with higher yields and performs high accuracy and robustness compared to state-of-the-art methods.
引用
收藏
页码:4196 / 4200
页数:5
相关论文
共 14 条
[1]   SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation [J].
Cho, Keonhee ;
Park, Juhyun ;
Kim, Kiryong ;
Oh, Tae Woo ;
Jung, Seong-Ook .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (03) :1567-1571
[2]   A SVM Surrogate Model-Based Method for Parametric Yield Optimization [J].
Ciccazzo, Angelo ;
Di Pillo, Gianni ;
Latorre, Vittorio .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (07) :1224-1228
[3]  
Finn C, 2017, PR MACH LEARN RES, V70
[4]   Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space [J].
Gao, Zhengqi ;
Tao, Jun ;
Su, Yangfeng ;
Zhou, Dian ;
Zeng, Xuan ;
Li, Xin .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (03) :789-793
[5]   Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs [J].
Gupta, Shourya ;
Calhoun, Benton H. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (03) :1171-1182
[6]   Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis [J].
Kwon, Hyunjeong ;
Kim, Daeyeon ;
Kim, Young Hwan ;
Kang, Seokhyeong .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (04) :1567-1577
[7]   An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis [J].
Shi, Xiao ;
Yan, Hao ;
Wang, Jinxin ;
Zhang, Jiajia ;
Shi, Longxing ;
He, Lei .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (12) :4999-5010
[8]   Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation [J].
Shi, Xiao ;
Yan, Hao ;
Huang, Qiancun ;
Zhang, Jiajia ;
Shi, Longxing ;
He, Lei .
PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,
[9]   Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space [J].
Sun, Shupeng ;
Li, Xin ;
Liu, Hongzhou ;
Luo, Kangsheng ;
Gu, Ben .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (07) :1096-1109
[10]   Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate [J].
Van Brandt, Leopold ;
Saeidi, Roghayeh ;
Bol, David ;
Flandre, Denis .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69 (07) :2767-2780