A fast ramp-up framework for wafer yield improvement in semiconductor manufacturing systems

Wafer yield is crucial for assessing semiconductor fabrication enterprises' stability and technological maturity. Quickly achieving the yield ramp-up of new products and timely feedback of failure analysis results to the design company are prerequisites for wafer fabrication factories to achieve stable mass production. However, the traditional wafer yield ramp-up process is time-consuming, and there is a high level of uncertainty in yield improvement even after parameter optimization. Therefore, a fast ramp-up framework for wafer yield improvement in semiconductor manufacturing systems is proposed to address both the aspect of temporal and the stability of yield enhancement. The Learning Cycle (LC) for yield acquisition, including fault detection, has been refined and optimized in the temporal dimension. Specifically, methods for multi-batch yield prediction and interpretability of defect traceability have been used to increase the LC efficiency. The yield enhancement dimension introduces a parameter optimization approach based on virtual metrology. This approach utilizes predictive control strategies to perform trial production verification with process parameters set to theoretical optima, thereby mitigating yield aberrant fluctuations in uncertainties inherent in the fabrication process and ensuring a consistent upward trajectory in yield levels with each iteration. The framework's efficacy is demonstrated using a case study focusing on yield control and enhancement within a specific wafer fabrication line. Applying the proposed framework shortened the ramp-up time from process design and pilot production to stable mass production, exhibiting an efficiency increase of nearly 17.6 %.