Fast-Locking Phase Locked Loop Dominated by SMC at VCO Voltage Tuning End

被引：0
作者：
Pu, Hongping [1 ,3 ]
Yang, Shiyong [2 ,3 ]
Xiong, Xingzhong [2 ,3 ]
Liu, Yongchun [2 ,3 ]
He, Jian [3 ,4 ]
Zheng, Xiaoxia [3 ,5 ]
机构：
[1] Chengdu Aeronaut Polytech, Sch Unmanned Aerial Vehicles Ind, Chengdu 610100, Sichuan, Peoples R China
[2] Sichuan Univ Sci & Engn, Sch Automat & Informat Engn, Yibin 644005, Sichuan, Peoples R China
[3] Sichuan Univ Sci & Engn, Artificial Intelligence Key Lab Sichuan Prov, Yibin 644005, Sichuan, Peoples R China
[4] Univ Elect Sci & Technol China UESTC, Yibin Inst, Yibin 644005, Sichuan, Peoples R China
[5] Chengdu Aeronaut Polytech, Sch Automot Engn, Chengdu 610100, Sichuan, Peoples R China
来源：
IEEE ACCESS | 2024年 / 12卷
关键词：
Voltage-controlled oscillators; Phase locked loops; Voltage control; Linear systems; Tuning; Switches; Charge pumps; Sliding mode control; Phase locked loop; sliding mode control; voltage control; PLL;
D O I：
10.1109/ACCESS.2024.3442291
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The presented fast-locking phase-locked loop (PLL) approach, driven by sliding mode control (SMC), aims to maintain defined design parameters and system stability while achieving faster frequency switching. By adding the SMC output control voltage to the tuning terminal of the voltage controlled oscillator (VCO), the PLL system achieves a higher absolute rate of change of the VCO output frequency during frequency hopping. Simulation results in Simulink demonstrate a significant reduction in locking time, from 40 mu s in the conventional PLL to 5 mu s in the proposed PLL, under identical conditions of loop bandwidth and charge pump current.
引用
收藏
页码：112135 / 112143
页数：9
相关论文
共 50 条
[41]   A 2 GHz phase-locked loop frequency synthesizer with on-chip VCO [J].
Ahola, R ;
Vikla, J ;
Lindfors, S ;
Routama, J ;
Halonen, K .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1999, 18 (01) :43-54
[42]   A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO [J].
Rami Ahola ;
Jyrki Vikla ;
Saska Lindfors ;
Jarkko Routama ;
Kari Halonen .
Analog Integrated Circuits and Signal Processing, 1999, 18 :43-54
[43]   Phase-error cancellation technique for fast-lock phase-locked loop [J].
Ding, Zhaoming ;
Liu, Haiqi ;
Li, Qiang .
IET CIRCUITS DEVICES & SYSTEMS, 2016, 10 (05) :417-422
[44]   Design of A Low Voltage Phase Locked Loop for Clock Generation [J].
Venkateswarlu, Mannem ;
Sarangam, K. .
2015 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, SIGNALS, COMMUNICATION AND OPTIMIZATION (EESCO), 2015,
[45]   Comparison and Optimization of Phase Locked Loop and Injection Locking Techniques for Optoelectronic Oscillators [J].
Zheng J.-C. ;
Jin T. ;
Chi H. ;
Tong G.-C. ;
Zhu X. ;
Lai T.-H. .
Guangzi Xuebao/Acta Photonica Sinica, 2017, 46 (04)
[46]   Fast Grid Voltage Synchronization using Modified Frequency-locked Loop in Single Phase Grid-connected Power Systems [J].
Hassanpour, H. ;
Ehsanian, M. .
INTERNATIONAL JOURNAL OF ENGINEERING, 2021, 34 (06) :1430-1437
[47]   Phase Error Analysis of Phase-locked Loop under Voltage Perturbation [J].
Hou, Chuanchuan ;
Zhu, Miao ;
Li, Zhengzhao ;
Cai, Xu .
2019 IEEE 4TH INTERNATIONAL FUTURE ENERGY ELECTRONICS CONFERENCE (IFEEC), 2019,
[48]   Impacts of Phase-Locked Loop Dynamic on the Stability of DC-Link Voltage Control in Voltage Source Converter Integrated to Weak Grid [J].
Huang, Yunhui ;
Wang, Lingyun ;
Zhang, Sidong ;
Wang, Dong ;
Deng, Xiangtian ;
Zhu, Guorong .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2022, 12 (01) :48-58
[49]   A single capacitor loop filter phase-locked loop with frequency voltage converter [J].
Jeong-hoon Nam ;
Young-Shig Choi ;
Moon G. Joo .
Analog Integrated Circuits and Signal Processing, 2013, 74 :193-201
[50]   A single capacitor loop filter phase-locked loop with frequency voltage converter [J].
Nam, Jeong-hoon ;
Choi, Young-Shig ;
Joo, Moon G. .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 74 (01) :193-201
12345