Grapher: A Reconfigurable Graph Computing Accelerator with Optimized Processing Elements

被引:0
|
作者
Deng, Junyong [1 ]
Lu, Songtao [1 ]
Zhang, Baoxiang [1 ]
Jia, Yanting [1 ]
机构
[1] Xian Univ Posts & Telecommun, Sch Elect Engn, Xian 710121, Peoples R China
基金
中国国家自然科学基金;
关键词
graph computing accelerator; reconfigurable computing; processing element array; parallel configuration; FRAMEWORK;
D O I
10.3390/electronics13173464
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, various graph computing architectures have been proposed to process graph data that represent complex dependencies between different objects in the world. The designs of the processing element (PE) in traditional graph computing accelerators are often optimized for specific graph algorithms or tasks, which limits their flexibility in processing different types of graph algorithms, or the parallel configuration that can be supported by their PE arrays is inefficient. To achieve both flexibility and efficiency, this paper proposes Grapher, a reconfigurable graph computing accelerator based on an optimized PE array, efficiently supporting multiple graph algorithms, enhancing parallel computation, and improving adaptability and system performance through dynamic hardware resource configuration. To verify the performance of Grapher, this paper selected six datasets from the Stanford Network Analysis Project (SNAP) database for testing. Compared with the existing typical graph frameworks Ligra, Gemini, and GraphBIG, the processing time for the six datasets using the BFS, CC, and PR algorithms was reduced by up to 39.31%, 35.43%, and 27.67%, respectively. The energy efficiency has also been improved by 1.8x compared to Hitgraph and 4.7x compared to ThunderGP.
引用
收藏
页数:12
相关论文
共 50 条
  • [1] Design of graph computing accelerator based on reconfigurable PE array
    Deng Junyong
    Jia Yanting
    Zhang Baoxiang
    Kang Yuchun
    Lu Songtao
    The Journal of China Universities of Posts and Telecommunications, 2024, 31 (05) : 49 - 63+70
  • [2] Design of graph computing accelerator based on reconfigurable PE array
    Junyong, Deng
    Yanting, Jia
    Baoxiang, Zhang
    Yuchun, Kang
    Songtao, Lu
    Journal of China Universities of Posts and Telecommunications, 2024, 31 (05): : 49 - 63
  • [3] GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing
    Angizi, Shaahin
    Fan, Deliang
    GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, 2019, : 45 - 50
  • [4] Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
    Olgu, Kaan
    Nikov, Kris
    Nunez-Yanez, Jose
    2022 25TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2022, : 16 - 23
  • [5] TuNao: A High-Performance and Energy-Efficient Reconfigurable Accelerator for Graph Processing
    Zhou, Jinhong
    Liu, Shaoli
    Guo, Qi
    Zhou, Xuda
    Zhi, Tian
    Liu, Daofu
    Wang, Chao
    Zhou, Xuehai
    Chen, Yunji
    Chen, Tianshi
    2017 17TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND GRID COMPUTING (CCGRID), 2017, : 731 - 734
  • [6] FPGAs as reconfigurable processing elements
    Bouldin, DW
    IEEE CIRCUITS AND DEVICES MAGAZINE, 1996, 12 (02): : 8 - 10
  • [7] DRGN: a dynamically reconfigurable accelerator for graph neural networks
    Yang C.
    Huo K.-B.
    Geng L.-F.
    Mei K.-Z.
    Journal of Ambient Intelligence and Humanized Computing, 2023, 14 (07) : 8985 - 9000
  • [8] High-performance computing using a reconfigurable accelerator
    Hartenstein, RW
    Becker, J
    Kress, R
    Reinig, H
    CONCURRENCY-PRACTICE AND EXPERIENCE, 1996, 8 (06): : 429 - 443
  • [9] A Multi-Grained Reconfigurable Accelerator for Approximate Computing
    Kan, Yirong
    Wu, Man
    Zhang, Renyuan
    Nakashima, Yasuhiko
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 90 - 95
  • [10] Towards Reconfigurable Optoelectronic Hardware Accelerator for Reservoir Computing
    Hasnain, Syed Ali
    Mahapatra, Rabi
    OPTOELECTRONIC DEVICES AND INTEGRATION IX, 2020, 11547