Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Degradation of SiC power mosfets under repetitive short-circuit (SC) stress is significant to the reliability of the power systems. A deep level transient spectrum method together with split C-V method to split the trap characteristics of the SiC mosfets is proposed. The degradation details of different locations in SiC planar gate (PG) and trench gate (TG) mosfets are comprehensively studied in this article. Thus, a criterion is provided to guide the SC degradation from the aspect of traps. The main degradation of the channel region is the increase of border traps for PG mosfet and newly generated interface traps for TG mosfet. The interface traps domain the degradation in the JFET region for both devices. The degradations of gate oxide for both devices affect the channel and JFET regions especially in the first set of SC cycles. The degradation of body diode is mainly influenced by hole traps in PG mosfet, but by electron traps first then hole traps newly generated in TG mosfet. Finally, the degradation locations of PG and TG mosfets are effectively characterized. It is the first time to use the trap measurement method to separate the different degradation in every part of the devices in detail. The method proposed in this article can better reflect the failure mechanisms related to dynamics and evaluate the operation of devices effectively, which provides very useful guidance for the reliability design and utilization of SiC mosfets.