Wafer and chip-level characterization of edge-coupled photonic integrated circuits by cascaded grating couplers and spot-size converters

被引：0

作者：

Eissa, Moataz ^{[1
]}

Sasaki, Ryuya ^{[1
]}

Horikawa, Tsuyoshi ^{[1
]}

Amemiya, Tomohiro ^{[1
]}

Nishiyama, Nobuhiko ^{[1
,2
,3
]}

机构：

[1] Tokyo Inst Technol, Elect & Elect Engn Dept, Tokyo 1528550, Japan

[2] Inst Innovat Res IIR, Tokyo Inst Technol, Tokyo 1528550, Japan

[3] Photon Elect Technol Res Assoc PETRA, Tokyo 1120014, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2024年 / 63卷 / 07期

关键词：

silicon photonics; testing process; grating coupler; spot-size converter; device characterization; photonic integrated circuit; SILICON; TECHNOLOGY;

D O I：

10.35848/1347-4065/ad5fd5

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

This study presents an efficient testing process for characterizing silicon photonic ICs. This process utilizes a coupling structure that integrates grating couplers and spot-size converters for efficient testing both at the chip and wafer levels, respectively. By leveraging wafer-level testing to estimate the characteristics of final chip-level devices, we anticipate a reduction in testing costs. To demonstrate the validity of the proposed testing process, we fabricated and measured silicon-on-insulator ring resonator devices on both wafer and chip levels. The results showed good agreement between the two levels of measurement, validating the effectiveness of our proposed testing process.

引用

页数：4