A 22-mW 0.9-2-GHz mixer-first receiver 8-phase overlap-suppressed 1/4 duty cycle LO for harmonic rejection

This paper presents a mixer-first wideband receiver front-end designed to achieve high linearity and harmonic rejection while minimizing power consumption. The proposed RF front-end adopts LO overlap suppression technology and uses 25 % duty cycle LO for 8-phase operation. In addition, the passive mixer with implicit capacitive stacking provides passive gain to the useful signal and improves harmonic rejection. The total power consumption of this work is less than 22 mW, the majority of which is consumed by the baseband amplifier and buffer, making it superior to existing active harmonic suppression RF front-ends in terms of low power consumption. The receiver is designed in TSMC 65-nm technology with an active area of 0.44 mm(2) and is suitable for various communication standards from 0.9 GHz to 2 GHz. Post-layout simulation results show that <-15 dB S11, 11 , 16.7-dBm OOB-IIP3@80 MHz, 3.7-6.7 dB DSB-NF, 46.4-49.5 dB total system voltage gain and HRR3 of 35.4-42 dB are achieved. No active components are required for harmonic recombination.