FSDedup: Feature-Aware and Selective Deduplication for Improving Performance of Encrypted Non-Volatile Main Memory

被引:0
作者
Du, Chunfeng [1 ]
Lin, Zihang [1 ]
Wu, Suzhen [2 ,3 ]
Chen, Yifei [1 ]
Wu, Jiapeng [1 ]
Wang, Shengzhe [1 ]
Wang, Weichun [4 ]
Wu, Qingfeng [1 ]
Mao, Bo [1 ]
机构
[1] Xiamen Univ, Sch Informat, Xiamen, Peoples R China
[2] Xiamen Univ, Sch Informat, Xiamen Key Lab Intelligent Storage & Comp, Xiamen, Peoples R China
[3] Wuhan Natl Lab Optoelect, Wuhan, Peoples R China
[4] Hikivision, Wuhan, Peoples R China
基金
国家重点研发计划;
关键词
Non-volatile main memory; ECC mechanism; content locality; selective deduplication; prefetch cache; refresh mechanism; WRITE;
D O I
10.1145/3662736
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Enhancing the endurance, performance, and energy efficiency of encrypted Non-Volatile Main Memory (NVMM) can be achieved by minimizing written data through inline deduplication. However, existing approaches applying inline deduplication to encrypted NVMM suffer from substantial performance degrada- tion due to high computing, memory footprint, and index-lookup overhead to generate, store, and query the cryptographic hash (fingerprint). In the preliminary ESD [14], we proposed the Error Correcting Code (ECC) assisted elective deduplication scheme, utilizing the ECC information as a fingerprint to identify similar data effettively and then leveraging the selective deduplication technique to eliminate a large amount of redundant data with high reference counts. In this article, we proposed FSDedup. Compared with ESD, FSD- edup cound leverage the prefetch cache to reduce the read overhead during similarity comparison and utilize the cache refresh mechanism to identify further and eliminate more redundant data. Extensive experimental evaluations demonstrate that FSDedup can enhance the performance of the NVMM system further than the ESD. Experimental results show that FSDedup can improve both write and read speed by up to 1.8x, enhance Instructions Per Cycle by up to 1.5x, and reduce energy consumption by up to 2.0x, compared to ESD.
引用
收藏
页数:33
相关论文
共 56 条
[1]   Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile Memories [J].
Abu Zubair, Kazi ;
Gurumurthi, Sudhanva ;
Sridharan, Vilas ;
Awad, Amro .
PROCEEDINGS OF 54TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2021, 2021, :1214-1226
[2]   Anubis*: Ultra-Low Overhead and Recovery Time for Secure Non-Volatile Memories [J].
Abu Zubair, Kazi ;
Awad, Amro .
PROCEEDINGS OF THE 2019 46TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '19), 2019, :157-168
[3]   Parity plus plus : Lightweight Error Correction for Last Level Caches [J].
Alam, Irina ;
Schoeny, Clayton ;
Dolecek, Lara ;
Gupta, Puneet .
2018 48TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS WORKSHOPS (DSN-W), 2018, :114-120
[4]  
[Anonymous], 2017, Qualcomm Centriq 2400 Processor
[5]  
[Anonymous], 2022, ECC for L2 Cache Data Memory
[6]  
[Anonymous], 2021, AMD EPYC Processors
[7]  
[Anonymous], 2023, Memcached
[8]   Triad-NVM: Persistency for Integrity-Protected and Encrypted Non-Volatile Memories [J].
Awad, Amro ;
Ye, Mao ;
Solihin, Yan ;
Njilla, Laurent ;
Abu Zubair, Kazi .
PROCEEDINGS OF THE 2019 46TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '19), 2019, :104-115
[9]   Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers [J].
Awad, Amro ;
Manadhata, Pratyusa ;
Haber, Stuart ;
Solihin, Yan ;
Horne, William .
ACM SIGPLAN NOTICES, 2016, 51 (04) :263-276
[10]  
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718