A 99.8-dB SNDR 10kHz-BW Second-Order DT Delta-Sigma Modulator with Single OTA and Enhanced Noise-Coupling

被引：0

作者：

Lu, Jiaju ^{[1
,2
]}

Zhang, Siqi ^{[1
,2
]}

Goh, Wang Ling ^{[1
]}

Gao, Yuan ^{[2
]}

机构：

[1] Nanyang Technol Univ NTU, Sch Elect & Elect Engn, Singapore, Singapore

[2] ASTAR, Inst Microelect IME, Singapore, Singapore

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

关键词：

Delta-sigma modulator; discrete-time; stage-sharing; noise-coupling; high-resolution; second-order;

D O I：

10.1109/ISCAS58744.2024.10557994

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a low-power second-order discrete-time (DT) Delta-Sigma Modulator (DSM) for Internet of Things (IoT) applications. The conventional noise coupling (NC) topology is improved with additional dual feedback paths to suppress the high-frequency gain of the noise transfer function (NTF), thereby reducing the internal voltage swing and relaxing the requirement of the quantizer resolution. In addition, stage-sharing technique is applied to reuse the OTA for both the integrator and the NC adder. Hence, second-order noise shaping is achieved with a single OTA. Implemented in a 130nm CMOS process, the proposed design demonstrated a simulated SNDR of 99.8dB in a 10kHz bandwidth with a 5.12MS/s sampling rate, consuming 200 mu W. State-of-the-art Schreier FoM (SNDR) and Walden FoM of 176.8dB and 125fJ/conv-step are achieved.

引用

页数：5

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