Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip

被引：0

作者：

Wang, Junjie ^{[1
]}

Liu, Shuang ^{[1
]}

Pan, Ruicheng ^{[1
]}

Yan, Shiqin ^{[1
]}

Liu, Yihe ^{[1
]}

Liu, Yang ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu, Peoples R China

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

关键词：

Computing-in-memory; Sparsity-aware readout; RRAM; Quantization-aware training;

D O I：

10.1109/ISCAS58744.2024.10558412

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a live demonstration of an RRAM processing-in-memory (PIM) chip in which the input sparsity is exploited to reduce power consumption and increase the throughput of the PIM chip. An offline quantization-aware training (QAT) is employed to fine-tune models to be suitable for the 4-bit PIM chip. Post-QAT, the model exhibited accuracy of 90.08% on the test dataset. Interestingly, we found that the input sparsity of input activation is always over 90%. This high level of sparsity proves advantageous, contributing substantially to both throughput and energy efficiency of the PIM chip. This design yields a throughput of 410 Gops, which is 9 times higher than the design without input sparsity awareness.

引用

页数：2