Device-Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors

被引：11

作者：

Swain, Peeyusha Saurabha ^{[1
]}

Shrivastava, Mayank ^{[2
]}

Gossner, Harald ^{[2
]}

Baghini, Maryam Shojaei ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

[2] Intel Corp, Mobile & Commun Grp, D-80336 Munich, Germany

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2013年 / 60卷 / 11期

关键词：

Device-circuit co-design; level shifter (LS); overlap region; shallow trench isolation drain extended MOS (STI-DeMOS); VOLTAGE; DRIVER;

D O I：

10.1109/TED.2013.2283421

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.

引用

页码：3827 / 3834

页数：8

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