A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers

被引:3
|
作者
Choi, Yohan [1 ]
Lee, Woojin [1 ]
Park, Sooho [1 ]
Kim, Changjoo [1 ]
Jung, Hyundo [1 ]
Kim, Chulwoo [1 ]
机构
[1] Korea Univ, Dept Elect Engn, Seoul 02841, South Korea
基金
新加坡国家研究基金会;
关键词
Capacitors; Circuits; Circuit stability; Noise; Timing; Three-dimensional displays; Stability criteria; Analog-to-digital converter (ADC); dynamic amplifier; floating inverter amplifier; fully dynamic ADC; Miller compensation; zoom ADC; SAR ADC;
D O I
10.1109/TCSII.2024.3392909
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a fully dynamic zoom analog-to-digital converter (ADC) using a Miller-compensated two-stage floating inverter amplifier (MCFIA). Due to the two-stage design, the proposed MCFIA achieves a sufficient gain for a high-resolution delta-sigma modulator design. Compared to the conventional two-stage design, the stability criterion of MCFIA is advantageous in driving bigger sampling capacitors needed to reduce kT/C noise. Moreover, a zoom ADC architecture mitigates the swing range requirement of the MCFIA. A prototype ADC was implemented in a 180-nm CMOS process and achieved a signal-to-noise and distortion ratio (SNDR) of 101.6 dB with an SNDR-based Schreier figure-of-merit of 174.8 dB at a sampling frequency of 2.56 MHz.
引用
收藏
页码:4141 / 4145
页数:5
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