Variation-aware automated design and optimization of sub-1V bandgap voltage reference

A robust systematic gm/ID-based design procedure for a CMOS low-voltage bandgap reference is introduced. The proposed approach is technology node independent, and it eliminates invoking the simulator in the loop by using precomputed lookup tables (LUTs) generated once. The proposed methodology is capable of addressing the impact of PVT corners and random mismatch. The proposed procedure is verified against Spectre simulations and yields very accurate results. Moreover, the bandgap reference automated synthesis procedure is fully vectorized, enabling the concurrent synthesis of multiple design points in a short time. As a result, large datasets can be generated to span the whole design space, which enables global optimization. Next, local optimization algorithms can be utilized to quickly determine the degrees of freedom of an optimal design point that meets a set of specifications. The speedup of the proposed methodology is around 140x compared to simulation-based optimization in addition to accomplishing better results.