A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE

被引：0

作者：

Hu, Xiaoyue ^{[1
]}

Lv, Fangxu ^{[1
]}

Lai, Mingche ^{[1
]}

Luo, Zhang ^{[1
]}

Wang, Qiang ^{[1
]}

Xu, Chaolong ^{[1
]}

Yin, Ruotian ^{[1
]}

Yang, Zhouhao ^{[1
]}

Liu, Cewen ^{[1
]}

机构：

[1] Dept Natl Univ Def Technol, Changsha 410000, Hunan, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2024年 / 21卷 / 19期

关键词：

equalizer; duobinary; PAM4; FFE; HPDFE; FPGA; LATENCY FEC DESIGN; WIRELINE TRANSCEIVER; DUOBINARY; PAM-4; NRZ; ADC;

D O I：

10.1587/elex.21.20240417

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The proposed equalizer introduces a dual-mode structure that can be utilized for decoding four-level pulse modulation (PAM4) and duobinary (DB) signals. The DB modulation is achieved by combining the NRZ signal output from the channel with continuous time linear equalizer(CTLE). Using feed forward equalizer (FFE) and hybrid parallel decision feedback equalizer (HPDFE) for equalization and decoding in digital signal processor (DSP). Test results based on analog-to-digital converter (ADC) and FPGA verification platform demonstrate that the proposed design is Of great significance for implementation. 28G@-43 dB nyquist channels are supported without a forward error correction (FEC) bit error rate (BER) of 1e-12 at 56 Gb/s.

引用

页数：6

共 4 条

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Lee, JH
Park, WH
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Sunwoo, MH
Kim, KH
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY, 2003, : 464 - 467
[2] A Novel Dual-Function Circuit Combining High-Speed Differential Equalizer and Common-Mode Filter With an Additional Zero
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Wu, Tzong-Lin
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2014, 24 (09) : 617 - 619
[3] A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications
Kim, Jae Joon
Cho, Chang-Hyuk
Chae, Kwan-Yeob
Byun, Sangjin
IEICE ELECTRONICS EXPRESS, 2011, 8 (20): : 1730 - 1735
[4] Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers
Azarderakhsh, Reza
Reyhani-Masoleh, Arash
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2015, 26 (06) : 1668 - 1677

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