A Wideband Timing Mismatch Calibration Design for Time-Interleaved Analog-to-Digital Converters with Fast Convergence

被引:0
作者
Huang, Guojing [1 ]
Xu, Dong [1 ]
Gao, Peng [2 ]
Zhou, Min [1 ]
Liu, Jiarui [1 ]
Wang, Zhiyu [1 ]
机构
[1] Zhejiang Univ, Sch Aeronaut & Astronaut, Hangzhou 310027, Peoples R China
[2] China United Network Commun Co Ltd, Jiangsu Branch, Nanjing 210019, Peoples R China
关键词
TIADC; fast convergence; LMS; wideband calibration; BACKGROUND CALIBRATION; SAR ADC;
D O I
10.3390/electronics13132459
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a design for timing mismatch calibration in a TIADC (Time-Interleaved Analog-to-Digital Converter) with wideband inputs. By exploiting the approximately linear relationship between the autocorrelation properties of sub-ADCs and timing mismatch, we achieve rapid convergence of error estimation. A low-cost detection method is proposed based on the convergent monotonicity of the Least Mean Square (LMS) algorithm, which can automatically correct the calibration direction when the input signal goes beyond the Nyquist zone. Physical test results indicate that the spurs caused by timing mismatch can be suppressed by 26-30 dB using the proposed method.
引用
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页数:12
相关论文
共 29 条
[11]  
Guo MQ, 2019, IEEE CUST INTEGR CIR, DOI [10.1109/CICC.2019.8780222, 10.1109/igsc48788.2019.8957195]
[12]   Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition [J].
Han Le Duc ;
Duc Minh Nguyen ;
Jabbour, Chadi ;
Desgreys, Patricia ;
Jamin, Olivier ;
Van Tam Nguyen .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (06) :1515-1528
[13]  
Janssen E, 2013, ISSCC DIG TECH PAP I, V56, P464, DOI 10.1109/ISSCC.2013.6487816
[14]   A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme [J].
Kang, Hyun-Wook ;
Hong, Hyeok-Ki ;
Kim, Wan ;
Ryu, Seung-Tak .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (09) :2584-2594
[15]   A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs [J].
Kang, Hyun-Wook ;
Hong, Hyeok-Ki ;
Park, Sanghoon ;
Kim, Ki-Jin ;
Ahn, Kwang-Ho ;
Ryu, Seung-Tak .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (06) :518-522
[16]  
Le Dortz N, 2014, ISSCC DIG TECH PAP I, V57, P386, DOI 10.1109/ISSCC.2014.6757481
[17]   A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration [J].
Lee, Sunghyuk ;
Chandrakasan, Anantha P. ;
Lee, Hae-Seung .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (12) :2846-2856
[18]  
Li DQ, 2018, 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), P53, DOI 10.1109/APCCAS.2018.8605698
[19]   A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration [J].
Li, Dengquan ;
Zhu, Zhangming ;
Ding, Ruixue ;
Liu, Maliang ;
Yang, Yintang ;
Sun, Nan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66 (01) :16-20
[20]   Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization [J].
Liu, Wenbo ;
Chiu, Yun .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (07) :1384-1395