An improved derivative-based phase-locked loop for single-phase grid synchronization under abnormal grid conditions

被引:1
作者
Hassan, Faridul [1 ]
Dubey, Alok Kumar [1 ]
Kumar, Amritesh [1 ]
Pati, Avadh [1 ]
机构
[1] Natl Inst Technol, Elect Engn Dept, Silchar, India
关键词
derivative-based phase-locked loop (DPLL); generalized integrator (GI); phase-locked loop (PLL); synchronization; PERFORMANCE ENHANCEMENT; ALGORITHM; PLL;
D O I
10.1002/cta.4211
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Generating a quadrature signal in a single-phase system using a second-order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase-locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI-PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI-PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI-PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade-off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative-based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single-phase grid synchronization under adverse grid conditions. The improved derivative-based PLL (IDPLL) comprises two improved derivative-based quadrature signal generator (IDQSG) blocks to extract the phase-error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real-time. The experimental results are obtained using an field programmable gate array (FPGA)-based controller. The standard second-order generalized integrator (SOGI)-based phase-locked loop (PLL) for single-phase systems relies on accurate frequency information, but grid abnormalities can disrupt its performance due to loop coupling phenomena and tuning sensitivity. To address these issues, an improved derivative-based PLL (IDPLL) is proposed based on the improved derivative-based quadrature signal generator (IDQSG) that eliminates the need for gain tuning and mitigates the loop coupling effects. The IDPLL offers enhanced dynamic performance and stability compared with the SOGI-PLL. Mathematical modeling and bode plot analysis of the IDQSG comparison with SOGI are provided, along with experimental validation using an field programmable gate array (FPGA)-based controller. image
引用
收藏
页数:16
相关论文
共 30 条
[1]   A Second Look on Nonfrequency-Dependent Transport Delay-Based PLL: Performance Enhancement Under Frequency Deviations [J].
Akhtar, Mohd Afroz ;
Saha, Suman ;
Singh, Ramandip .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2021, 36 (12) :13365-13371
[2]   An Adaptive Frequency-Fixed Second-Order Generalized Integrator-Quadrature Signal Generator Using Fractional-Order Conformal Mapping Based Approach [J].
Akhtar, Mohd Afroz ;
Saha, Suman .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2020, 35 (06) :5548-5552
[3]   Parameter Estimation and Grid Synchronization Using a First-Order Frequency-Locked Loop [J].
Bamigbade, Abdullahi ;
Khadkikar, Vinod .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2022, 71
[4]  
Ciobanu Monica., 2005, PAPER RESENTED ANN M, P1
[5]   A new single-phase PLL structure based on second order generalized integrator [J].
Ciobotaru, Mihai ;
Teodorescu, Remus ;
Blaabjerg, Frede .
2006 IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE, VOLS 1-7, 2006, :361-+
[6]   Robust phase locked-loop algorithm for single-phase utility-interactive inverters [J].
Elrayyah, Ali ;
Sozer, Yilmaz ;
Elbuluk, Malik .
IET POWER ELECTRONICS, 2014, 7 (05) :1064-1072
[7]   A Frequency-Locked-Loop Filter for Biased Multi-Sinusoidal Estimation [J].
Fedele, Giuseppe ;
Ferrise, Andrea .
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2014, 62 (05) :1125-1134
[8]  
Fyen S., 2020, Singlephase synchronisation with hilbert transformers: a linear and frequency independent orthogonal system generator, P1
[9]  
Galkin I, 2015, IEEE IND ELEC, P4538
[10]   Single-Phase Frequency-Locked Loops: A Comprehensive Review [J].
Golestan, Saeed ;
Guerrero, Josep M. ;
Musavi, Fariborz ;
Vasquez, Juan C. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2019, 34 (12) :11791-11812